7 ms·

the significance and allure of risc-v, the reason china is investing heavily in it right now, has little to do with the technical details of how it works under

• zephen 1mo ago
  > it's the fact that it is an open standard not encumbered by intellectual property law. There are actually many of those. But Risc-V has become, through effective marketing, the Schelling point for anybody who wants to avoid the x86 and Arm ecosystems, both for the rent-seeking behaviors you mention, and also, in some instances, for security reasons. And, as others have mentioned, the ISA doesn't really matter. As long as it's agreed upon, then the CPU vendors can optimize on one side, and the compiler writers on the other side. Sure, Risc-V has its warts, but you can certainly say the same about all the rest.
  • mhh__ 1mo ago
    The ISA not mattering I think isn't as true when you account cost e.g. in a huge OOO cpu all the fusions and so on are afaict fairly doable but if you are on a cheaper / worse CPU all those extra bytes in the instruction stream do add up.
    • wren6991 1mo ago
      The RISC-V fusion arguments from back in ~2018 didn't really pan out. A lot of those fusion opportunities are just instructions now. slli + add? Zba (sh*add). slli + srli? Zbb (zext.*). slli + srai? Believe it or not, also Zbb (sext.*). Look at that pair of RVC instructions you used instead of a single 32-bit opcode. They are: * Taking up valuable compressed instruction space; each compressed codepoint has an opportunity cost of 64k uncompressed ones. * Limited in which registers they can use (usually x8..x15). * Often clobber their input operand instead of giving a free move. Also consider that the frequency data that drove the RVC compression decisions was driven by the lack of architecturally fused instructions like sh*add, so any arguments you derive from that data are circular. An instruction can be a good uarch fusion target because it's compressed, and a good compression target because you didn't fuse it in the architecture. I think designing for uarch fusion in your ISA is coming at it from the wrong end. Fusion is something uarch designers do to make up for shortcomings in the ISA.
      • brucehoult 1mo ago
        And all modern high performance Arm and x86 cores do more fusion than RISC-V cores that are currently on the market. Intel has being fusing `CMP` and `Bcc` since Core 2 and AMD since Zen 1. This is - already one instruction in RISC-V - an *extremely* common pattern, often occurring once every 5 or 6 instructions.
        • adrian_b 1mo ago
          The combined comparison-branch instructions of RISC-V are its only good feature in terms of instruction encoding design. This allows a significant code size reduction in comparison with ARM Aarch64, but unfortunately for RISC-V this advantage is frequently not enough to compensate its other defects, especially when reliable code is desired, i.e. where overflow detection is necessary. Despite that from this point of view ARM Aarch64 is weaker, that is not an intrinsic problem. Aarch64 has an unused block of encodings inside the block used for branch instructions. I have verified that in the currently unused block it is possible to encode not only compare-and-branch instructions covering all the conditions that exist in the RISC-V ISA, but also additional conditions that are missing in RISC-V, where their absence is a problem, like testing for overflow. I do not know why nobody at Arm had thought to make this extension yet, but it would be very easy to eliminate the only advantage that RISC-V has over Aarch64.
          • zephen 1mo ago
            > I do not know why nobody at Arm had thought to make this extension yet, but it would be very easy to eliminate the only advantage that RISC-V has over Aarch64. Nope. Again, the primary advantage that RISC-V has over Aarch64 is that it is the agreed-upon open specification.
            • brucehoult 1mo ago
              Also I haven't looked closely but I don't know if you could find space to fit it in the remaining Aarch64 encoding space. The existing a64 conditional branch instructions use a 19 bit field to hold the offset. Add two registers to compare (10 bits) and 3 bits to choose between EQ, NE, LT, LTU, GE, GEU and you're already at 32 bits before having an "opcode" field to choose "RISC-V style conditional branch". Of course you could reduce the branch offset size down to RISC-V's ±4k which only needs 11 bits when you only have 4 byte instructions, but that's still a 24 bit chunk of unused opcode space to find. Oh .. looks like 0b10xx is still completely unused. We could grab maybe 1/4 of it So could do ... [31:28] (4 bits): 0b1000 (Fixed primary opcode .. or 0b1001, 0b1010, 0b1011) [27:23] (5 bits): Rs1 [22:18] (5 bits): Rs2 [17:15] (3 bits): Cond (EQ, NE, LT, GE, LTU, GEU, + possible 2 more) [14:4] (11 bits): Offset (Signed ±4k PC-relative offset) [3:0] (4 bits): 0b0000 (Fixed minor opcode/extension identifier) One problem here is this doesn't allow both 32 bit and 64 bit compares. And also the Rs1 and Rs2 are not in the usual places. Maybe... [31:28] (4 bits): 0b1000 (Fixed primary opcode) [27:21] (7 bits): Offset[12:6] [20:16] (5 bits): Rm [15:13] (3 bits): Cond (EQ, NE, LT, GE, LTU, GEU, etc) [12:10] (3 bits): Offset[5:3] [9:5] (5 bits): Rn [4:2] (3 bits): Offset[2:0] [1] (1 bit): sf (Size flag: 0 = 32-bit compare, 1 = 64-bit compare) [0] (1 bit): 0b0 (Fixed) I think this fits other instruction formats better .. and gives a ±16k branch range. Some ::coff:: would criticise the split up offset field. Not RISC-V fans of course. And this puts sf in a non-standard place. Some more playing around is needed .. over to you Arm.
    • brucehoult 1mo ago
      Performance is subject to debate and quality of implementation and whether such implementations will ever be financed and made ... But *code size* is a demonstrable fact. RISC-V has by far the most compact code of any popular 64 bit ISA, and that was true even of RV64GC. The gap has only widened with RVA23. Just load up your favourite OS (e.g. Ubuntu 26.04) for various ISAs in Docker and compare the `text` size of various binaries, individually or in aggregate. In 32 bit ARMv7-M / ARMv7-A had a small code size lead over RV32IMAC, but this is reversed in modern RISC-V e.g. if you look at RISC-V Hazard3 vs Arm Cortex-M33 in the RP2350 (Raspberry Pi Pico 2) where you can trivially change one option setting in your project and recompile and test. The only exception is that the M33 has a single-precision FPU, which neither the Hazard3 nor the Cortex-M0+ in the RP2040 have.
      • dmitrygr 1mo ago
        > RISC-V has by far the most compact code of any popular 64 bit ISA, Forgot to say “RISC”. Cause else: amd64
        • brucehoult 1mo ago
          No, RISC-V code is much more compact than Amd64. This is easily demonstrated on any real application, such as those in your favourite Linux distribution.
      • adrian_b 1mo ago
        That is false. All the claims of the RISC-V fans that I have seen in the past compared the compressed variant of RISC-V with the uncompressed variants of the other ISAs. Most other ISAs, like ARM, POWER and MIPS, also have compressed variants and if RISC-V were compared with those, it would lose. Moreover, if you use safe compilation options with RISC-V, the code size explodes in comparison with any other ISA, because I am not aware of any other ISA introduced after 1974 that lacks hardware overflow detection, which multiplies by 3 or more the number of arithmetic instructions required for any computation. This is a new claim that I see now, that RISC-V can be more compact than Cortex-M33 (i.e. where both use a compressed encoding), which I find unbelievable, because if I assembly by hand almost any function that is not too simple I can make it shorter on Cortex-M33 than on RISC-V and I doubt that the current compilers are so bad that they generate much worse code. RISC-V is shorter on any code that has a lot of branches and negligible computations, but for anything more complex, with many computations and complex data structures, it loses.
  • hn_submit 1mo ago
    x86 is basically one big cabinet of horrors, but people seem to put up with it because it's "the standard." Then why not with RISC-V? Which is much if not infinitely better.
    • IcyWindows 1mo ago
      The article explains why it's worse
      • zephen 1mo ago
        The article explains why the author believes it's worse.
  • inkyoto 1mo ago
    > […] then the CPU vendors can optimize on one side […] I find the statement ironic and somewhat amusing (or bemusing – depending on the perspective) for reasons entirely unrelated to CPU's and/or RISC-V. I keep hearing the phrase «we shall leave that to the vendors» every now and then. Only a few days ago, whilst attending a working-group session on an emerging data exchange standard, precisely the very much same argument was bluntly stated: «We do not particularly care how complex the specification becomes because the vendors will implement it. We shall leave it to them». The issue is that «the vendors» are not a single mythical intelligence or force possessed of infinite technical wisdom, unlimited, cosmic scale engineering resources and an relentless desire to right the wrongs. They are businesses. They have narrow commercial objectives, conflicting priorities, disparities in the engineering talent and resourcing and, quite properly, incentives to advance their own products – you are right, to compete with other vendors. Where an opportunity appears to increase market share, lock customers in, differentiate their platforms and products or shift implementation burden elsewhere, one should expect them to notice it. It is not an accusation, it is merely an acknowledgement that vendors tend to behave like vendors. So with «the vendors will do X», at best, we may hope that vendors will deliver an interpretation of the specification – to a degree, provided that doing so aligns sufficiently well with their commercial interests. An equally plausible outcome is that they will not – or that they will each implement mutually incompatible interpretations whilst proclaiming full compliance.
    • zephen 1mo ago
      > I find the statement ironic, What you find may or may not match reality. In this instance, I don't believe it does. > We do not particularly care how complex the specification becomes because the vendors will implement it. We shall leave it to them. This, of course, is a silly argument. Yet, it is completely orthogonal to the one I was making, and is 180 degrees away from the complaints leveled at Risc-V which are that it is an overly simplistic, nay childish, specification, written in crayon by kindergartners. > The issue is that «the vendors» are not a single mythical intelligence or force possessed of infinite technical wisdom, unlimited, cosmic scale engineering resources and an relentless desire to right the wrongs. I find this statement accurate, yet condescending. Who the fuck thinks that they are? Claiming that this is an "issue" with my statement appears to be a reductive argument that I have not thought it through. To be blunt, this statement reveals a hell of a lot more about your ignorance on this issue than mine. > It is not an accusation, it is merely an acknowledgement that vendors tend to behave like vendors. And yet, we have seen this play out in x86, with Intel v. AMD, and it worked exceptionally well. > An equally plausible outcome is that they will not – or that they will each implement mutually incompatible interpretations whilst proclaiming full compliance. Of course, AMD and Intel were always trying to one-up each other, but that is tempered by the necessity for their improvements to be supported by compilers. By the time an improvement is well-supported, the other side has caught up. With Risc-V this is even more likely to be the case, because proprietary extensions will simply not be that well supported by major compiler vendors, who have a hard enough time keeping up with the ratified ones.
• rayiner 1mo ago
  Isn't almost everything in MIPS long outside patent protection?
  • bjornnn 1mo ago
    even when foundational patents expire, licensing agreements and copyright and trademark and other things remain legally enforceable. chinese companies actually did start investing in mips at one point but ended up getting sued. people tried to open source mips years ago but gave up and just switched to risc-v because it's too much of a legal hassle to try to open source something that was proprietary for decades and has all the legacy baggage of multiple previous owners who want to sue you for any reason they can think of. it was easier to just design a new architecture that was open from the start.
  • genxy 1mo ago
    I think the issue is then, if you have the same base lineage and you start extending and fixing things, then it will be easy to overlap with new patents that whomever still holds MIPS IP. RISC-V is mainly a way to avoid IP conflicts, not as a technical breakthrough. MIPS itself was a boring (this is good) implementation of the original RISC papers, but they asserted a bunch of things legally which eventually, along with the legal work of Arm meant that ISAs were effectively owned by their parent corporations. I'd assert that much like 3rd parties being able to make replacement car parts, that we should be able to make ISA compatible chips. But here we are, RISC-V needs to exist and does, but for legal reasons, not technical ones. *edit, I forgot to refresh before posting, what bjornnn said.
• dismalaf 1mo ago
  It's not just China that has an interest. Multinational corporations also hate being charged licensing fees (see Qualcomm vs. ARM). Here's a list of RISC-V members: https://riscv.org/members/ https://riscv.org/members/
  • mcdow 1mo ago
    lol the government of brazil is in there
    • Narishma 1mo ago
      Why is that funny?
      • mcdow 1mo ago
        it’s funny because it’s unexpected. one of those members is not like the others. the rest are tech companies. it does make me wonder what prompted them to join. it would suggest to me there are forward looking people in Brazil’s government. I am impressed.
        • koverstreet 1mo ago
          I consistently see a level of competence and professionalism in South America that has left the building in the states.