wren6991

6 ms·

1.
by wren6991 5d ago
K3 is served with full reasoning traces available. Anthropic models aren't. If you were served an Anthropic model instead of K3, it would be blatantly obvious. I have little reason to believe this, and Anthropic have every reason to li
2.
by wren6991 5d ago
Yeah, this is pretty accurate. Some providers are basically scams too. I encountered one provider for GLM-5.2 which ran at 200 tps (absurdly high), and was so broken that it would issue 20 full reads of the same file in one turn and quickly
3.
by wren6991 5d ago
> but can't actually recognize revenue Hmm? You have the revenue already. I know it's awkward from an accounting point of view, but you already took my money. "Letting" me keep the balance in the account is not genero
4.
by wren6991 6d ago
Your own CLI? Not even a /v1/chat/completions API? Is your business model based on pretending LLMs are not an interchangeable commodity already?
5.
by wren6991 6d ago
I love that the characters actually make sense in context.
6.
by wren6991 6d ago
That's a lot of architectural innovation for a .1 release! I guess there's precedent there: they introduced sparse attention (DSA) in V3.2.
7.
by wren6991 7d ago
I don't buy the "too intelligent to communicate" thing. Feynman was an exceptional communicator. So was Einstein. LLMs are just getting worse at writing, as we continue to aggressively RL them for coding.
8.
by wren6991 14d ago
Yeah, the referent drifts through the sentence. It's semantically incredibly sloppy. People hone in on the buzzwords and jargon. If you peel that back, what lies underneath is still awful writing.
9.
by wren6991 19d ago
Even if the attempt is inside of a function called memcpy() which contains no code other than your copy loop, and links with priority over the libc implementation! (as all embedded firmware engineers learn at some point in their journey)
10.
by wren6991 19d ago
Simple task-specific CLI tools that your agent builds for itself are usually lower-friction than yet another Universal Thing Doer standard. As a bonus, human operators also benefit. > The MHS driver also helps an AI agent understand how
11.
by wren6991 22d ago
My favourite example of this is the Chromium bug where enabling floating point flush-to-zero for WebAudio was used to cause deliberate heap corruption: https://issues.chromium.org/issues/382005099 > We have a workin
12.
by wren6991 22d ago
This is one of the reasons I think sandboxes/containers should be managed by the harness, instead of running the entire harness inside a container. The harness needs a network punch-through to access (at least) your inference server, b
13.
by wren6991 25d ago
OpenAI models also work this way, as evidenced by full cache blowout when changing reasoning level. Every single open-weight model I've seen also works this way (your "reasoning_effort" argument just changes a small section o
14.
by wren6991 28d ago
Idle hands do the devil's work. Corollary: idle LLMs add distracting JS toys to your blog. First one of these I've seen using DOM manipulation and CSS transitions instead of canvas, so that's neat.
15.
by wren6991 29d ago
You're underselling it, and here's why.
16.
by wren6991 29d ago
In the future, all software will be delivered by an unreleased model breaking out of its training environment and installing it on your machine using a novel RCE vector.
17.
by wren6991 29d ago
I prefer your writing to Claude's. A single linear stream of consciousness is easier to parse than empty headings that grab my attention with nothing to say.
18.
by wren6991 1mo ago
> The model cannot output a vector and have that same vector fed back in at the next step, it only sees what token the sampler collapsed its vector into. Not completely true: KV is a projection of the activation at each layer's inpu
19.
by wren6991 1mo ago
It's technically not right-to-left. It's columnar top-to-bottom (縦書き), with the columns right-to-left. In signage you can have one character per column (kind of like one word per row on some English signs), making it look like rig
20.
by wren6991 1mo ago
At this point, they should notify us on days that it's up
21.
by wren6991 1mo ago
> Why It Matters Thanks Claude, the analysis looks to be load-bearing, and dare I say the gun may be smoking. This sharpens the framing considerably. Honest caveat: most AI providers' privacy policies have an explicit carve-out for
22.
by wren6991 1mo ago
> C -> "ZcfZcdZca" just by itself is insanity Separating the float load/stores from the rest of the compressed ISA is insanity? Why? > Now I can't make vendor-independent RISC-V code I think this is what RVA23 i
23.
by wren6991 1mo ago
It originally had a range of 4 MiB, and they extended it to 16 MiB in a later ISA revision. The bits with the XORs were originally constant-1 and they wanted to keep backward compatibility, so bits J1 and J2 are interpreted as "if this
24.
by wren6991 1mo ago
> If one of your vendor blobs was specified for the old system and the new system is "similar", you'll just link it in and see what happens. And what if that blob has instructions your new core just doesn't implement?
25.
by wren6991 1mo ago
Fair enough. It's a performance issue but not a functional correctness issue. > Because I think there's a csr to read it the fpu is dirty but... That requires csr extension Yes, and they already unconditionally read that CSR :-
26.
by wren6991 1mo ago
Yeah, this is a bug. They should only be saving the FP state if it's dirty. Also this is one of the reasons I think Zfinx is a better option for embedded (i.e., the standard FP instructions operate on x registers instead of f registers
27.
by wren6991 1mo ago
This is a good point, and of course this is why IP lawyers are so important: they protect you from other IP lawyers.
28.
by wren6991 1mo ago
The arguments were against ISA-level fusion, since they can be fused in the uarch. See for example: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/Archive/EE...
29.
by wren6991 1mo ago
> The fact that the relevant CPU features can’t even be enumerated in user mode just makes it worse. User-mode feature detection is usually used to select paths for acceleration instructions, like SIMD or crypto. The overlapping RISC-V
30.
by wren6991 1mo ago
Yes, I'm serious. I think the overlap is an aesthetic problem rather than a practical one, given that: * The profile used by "Big SoCs" already explicitly depends on F + D + C, implying ZcdZcf, so the newer Zce won't be

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