brucehoult

8 ms·

1.
by brucehoult 13d ago
If it's a pro then they'll be sitting in the back seat so you're in the front seat the same as you will be when you fly solo. Here's a video of me taking a student for their first lesson: https://www.youtube.c
2.
by brucehoult 13d ago
In sailplanes we add up to around 200 litres of water to wing tanks in single-seat gliders (empty weight typically around 280kg) to improve the high speed performance (typically up to 270 km/h these days) and ability to fly comfortably
3.
by brucehoult 14d ago
Many rather wide streets in the centre of New Zealand cities have had 30 km/h speed limits since ... I think the 1990s. For example here, Willis St in Wellington: https://maps.app.goo.gl/8hHCLxCDK4C8U8Tz9 You can see i
4.
by brucehoult 20d ago
I guess you missed Leela then. And in 2020 Stockfish 12 adding some NN evaluation. And then in 2023 Stockfish 16 entirely removing the classical position evaluation code. https://stockfishchess.org/blog/2023/stockf
5.
by brucehoult 22d ago
Or Mojo, recently acquired by Qualcomm, and even more recently fully open-sourced under Apache 2 license.
6.
by brucehoult 22d ago
That's how it works, yes, if the originator makes it freely available then so does ISO.
7.
by brucehoult 25d ago
The 256 byte hardware stack is plenty for function return addresses and temporary use within a function. How deep are you planning to nest function calls anyway? You can create as many other stacks as you want using pairs of Zero Page locat
8.
by brucehoult 25d ago
> I still prefer programming the Z80 over the 6502 though :) I really don't. There are some few things you can fit into and get working fast in the Z80's A + 6 registers (IX and IY are not useful if speed is the aim), but for a
9.
by brucehoult 1mo ago
Also I haven't looked closely but I don't know if you could find space to fit it in the remaining Aarch64 encoding space. The existing a64 conditional branch instructions use a 19 bit field to hold the offset. Add two registers to
10.
by brucehoult 1mo ago
SVE2 is compulsory in ARMv9-A, but NEON is optional?
11.
by brucehoult 1mo ago
C-Sky and Andes NDS32 were popular enough to be supported by both GCC and the Linux kernel, both switched to RISC-V. ESP32 switched to RISC_V for all new chips. Interestingly Synopsys's ARC's latest version ARC-V is RISC-V. I thin
12.
by brucehoult 1mo ago
Why? It'll still run fine. Just like Debian still runs on original x86-64-v1 from 1999, not x86-64-v3 (needs AVX2,FMA, BMI1, BMI2, LZCNT) or even x86-64-v3 (needs AVX-512). Similarly, Debian for arm64 still requires only ARMv8.0-A from
13.
by brucehoult 1mo ago
Not me for sure. I have no idea about you. Of household name companies I've only worked at Mozilla and Samsung R&D. And SiFive if you count people in threads such as this. I could of course be wrong but I think the publicly known h
14.
by brucehoult 1mo ago
Such as? There is still plenty of unused 32 bit (30 bit) opcode space.
15.
by brucehoult 1mo ago
I specified "popular 64 bit ISA", which comes down to amd64 and arm64. But you can include Elbrus and LoongArch if you want. Or POWER. Or Itanium. > I assembly by hand almost any function that is not too simple I can make it sh
16.
by brucehoult 1mo ago
You can choose Arm in one pair and RISC-V in the other pair if you want.
17.
by brucehoult 1mo ago
No, RISC-V code is much more compact than Amd64. This is easily demonstrated on any real application, such as those in your favourite Linux distribution.
18.
by brucehoult 1mo ago
It's not even double, because half of them are RVC-only decoders.
19.
by brucehoult 1mo ago
And Arm dropped a T16-like encoding entirely from their 64 bit instruction set. If they did everything exactly the same they would be the same ISA not different ISAs. It's just as easy to point to things that RVC can do that T16 can&#x
20.
by brucehoult 1mo ago
There is zero chance that Apple doesn't have MacOS and iOS running on RISC-V in the lab. They did that with x86 and Arm half a decade before any announcement about a switch, not to mention a number of other ISAs that didn't make i
21.
by brucehoult 1mo ago
History is much easier than prediction. I'm with Jim Keller when he says that in time the fastest CPUs will be RISC-V ones.
22.
by brucehoult 1mo ago
> you can use the same base trick behind a carry lookahead adder YESSSS. I've been pointing this out for years and years. By the point that you're looking at the same propagation delay as a common 64 bit adder you're decod
23.
by brucehoult 1mo ago
It's not wasted when it makes programs overall smaller, as it does.
24.
by brucehoult 1mo ago
Ubuntu 24.04 LTS exists and needs only RV64GC and will be supported and enhanced for many more years. Debian has no plans to require more than RV64GC. RVA23 is a very good thing in certain markets, but nothing forces you to support it for a
25.
by brucehoult 1mo ago
And all modern high performance Arm and x86 cores do more fusion than RISC-V cores that are currently on the market. Intel has being fusing `CMP` and `Bcc` since Core 2 and AMD since Zen 1. This is - already one instruction in RISC-V - an *
26.
by brucehoult 1mo ago
Performance is subject to debate and quality of implementation and whether such implementations will ever be financed and made ... But *code size* is a demonstrable fact. RISC-V has by far the most compact code of any popular 64 bit ISA, an
27.
by brucehoult 1mo ago
Luke is too modest. Something in the region of 5 million chips containing his hobby CPU have shipped since launch on August 8, 2024.
28.
by brucehoult 1mo ago
In the distant past (2002-2003) I used two niche languages for the same programs across PowerPC, x86, SPARC, and PA-RISC: - Dylan - Scheme It helped immensely that both Gwydion Dylan and Chicken Scheme compile their respective niche languag
29.
by brucehoult 1mo ago
BASE jumpers and wing suit fliers too.
30.
by brucehoult 2mo ago
On my SpacemiT K3 SBC with 32GB RAM (where models run on the eight A100 RISC-V cores with 1024 bit vectors) doing the same task I got 5, 5.8, 6.5 tok/s using gemma-4-26B-A4B-it-QAT-Q4_0.gguf, Qwen3.6-35B-A3B-Q4_K_M.gguf, Qwen3.5-35B-A3

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