camel-cdr

5 ms·

1.
A "proof" of Fermat's Last Theorem that fits the margin(blog.trailofbits.com)
8 points by camel-cdr 7d ago|0 comments
2.
by camel-cdr 8d ago
https://reddit.com/r/IndieDev/comments/1vfwuf5/a_player_foun...
3.
by camel-cdr 8d ago
I found this post interesting in that reguard: https://www.lesswrong.com/posts/thXohzXrWCA2EhZCH/mateusz-ba...
4.
by camel-cdr 8d ago
There also is an insentive to silently give prominent people (e.g. Linus) or reasearchers like this custom tuned system prompts or even more powerful models.
5.
by camel-cdr 12d ago
I suppose nobody sane would give their AI internet access (even read) while training it. Though if they did, I don't think they'd want this to be public, because how can you even protect against this?
6.
by camel-cdr 18d ago
I wonder how much this matters for python. As long as the important dependencies like numpy runtime dispatch RVV, it should probably be fine. Zba would probably give a small boost. Zbb gives a substantial boost to perf for applications that
7.
by camel-cdr 23d ago
https://camel-cdr.github.io/rvv-bench-results/sifive_p870/in...
8.
by camel-cdr 23d ago
related: https://www.sifive.com/development-platforms/sifive-bigsky-s...
9.
ISO/IEC DIS 26791-1 – The RISC-V instruction set manual(iso.org)
4 points by camel-cdr 23d ago|3 comments
10.
by camel-cdr 25d ago
I really like what you are doing here, the state of inline assembly is a similar travesty to the state of guided codegen/autovec. On concern I have is how this maps to ARM64 syntax, because ARM64 is massively overloading all mnemonics.
11.
by camel-cdr 25d ago
> I was aware that some architectures had distinct floating point registers Most ISAs do. On x86 and arm scalar and FP registers are separate, it's just that they overlap FP and SIMD registers. On RISC-V there are three separate reg
12.
by camel-cdr 28d ago
Already in the works: https://lists.riscv.org/g/tech-announce/message/782
13.
by camel-cdr 1mo ago
The P870 is probably faster than the Cortex-X1 in my phone, which would put it on a similar per level to Zen1. When I had brief access to a very early P870 devboard running at 2GHz it scored 2% worse than an 2.86GHz Cortex-X1 in the 7-zip b
14.
by camel-cdr 1mo ago
I think it will be closer to Zen 1/2
15.
by camel-cdr 1mo ago
Great news! How did I miss that? I'll have to try out the branch.
16.
by camel-cdr 1mo ago
Which may actually be a good analogy. One thing I've seen rarely discussed is existing expertise/experiance, existing varification/tooling and existing quality reference implementations. Arm wins in all of the above over RISC
17.
by camel-cdr 1mo ago
I basically spend way to much time with RISC-V related things. But the easiest way to get more info about RISC-V developmemts is by watching the youtube uploads of the RISC-V summit talks.
18.
by camel-cdr 1mo ago
Here are a few random things I know of: * Tenstorrent Ascalon has a neat optimization for certain LMUL>1 SIMD operations. LMUL=2 effectively unrolls the SIMD operation making it read two SIMD registers from every source and write two SIM
19.
by camel-cdr 1mo ago
https://support.arm.com/documentation/109697/2026_06/Feature... > In an Armv9.0 implementation, if FEAT_FP and FEAT_AdvSIMD are implemented, the following features are implemented: ... This implies they do
20.
by camel-cdr 1mo ago
Did a quick grep over object files of a half build defconfig kernel: total: 15510 #0: 3720 #31: 2247 #1: 1349 #21: 1208 #2: 810 #3: 524 #8: 493 ...
21.
by camel-cdr 1mo ago
> Adding a flags register doesn't really add any more complexity, it's just a small bit of extra state attached to it. I agree in general, we do however see that the cost of flags isn't free by the fact that most modern Ar
22.
by camel-cdr 1mo ago
No, debian requires ARMv8.0-A + FP + NEON, as those are optinal extensions (even optional in ARMv9.0-A)
23.
by camel-cdr 1mo ago
> You shouldn't be sharing that Ah, I suppose.
24.
by camel-cdr 1mo ago
Edit: removed Yeah, fusing is probably easier, if you already know what to fuse. On the other hand, if you want to fuse load pair on RISC-V you have the entire rename stage to figure out which uops can be fused independently of the rename s
25.
by camel-cdr 1mo ago
> While smaller cores have the option of cracking the multiple writeback instructions, many arm cores just pay the extra cost of having a 3 read, 2 write register file, so they aren’t actually cracking those instructions. No, every high
26.
by camel-cdr 1mo ago
The decoder decodes them into two or more internal instructions (uops). Take for example a post increment load, which does a=mem[b++], notice how this writes to two registers. Handeling two writes (up to 4) would explode the stage after dec
27.
by camel-cdr 1mo ago
I want to try looking at codesize for -Os builds with the different ISAs including the compressed variants you mentioned. As well as dynamic icount with overflow checking. Do you have any specific project in mind that I could use for testin
28.
by camel-cdr 1mo ago
https://github.com/riscv/riscv-isa-manual/pull/3269
29.
by camel-cdr 1mo ago
The RVA point releases don't add new mandatory features, so every RVA23 complient board is also RVA23.1 complient. They only add new optional extensions.
30.
by camel-cdr 1mo ago
There is a very easy way to determine what hardware you are running on, it's the baseline of the OS. Armv9-a doesn't mandate FP or SIMD support, but nobody does detection for those, why? Because it's required on the OS level.

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