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Aegis – open-source FPGA silicon
- blowback 6mo agoExcellent. Put me down for a couple.
- morphle 6mo agome too please
- rosscomputerguy 6mo agoPlease vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11 https://github.com/MidstallSoftware/aegis/discussions/11
- rosscomputerguy 6mo agoPlease vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11 https://github.com/MidstallSoftware/aegis/discussions/11
- Bluebirt 6mo agoNeat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work. But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
- __patchbit__ 6mo ago[flagged]
- LarsKrimi 6mo agoThis project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz If those numbers are at all right it puts it in useful territory. Very much so for a first spin For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)
- rosscomputerguy 6mo agoThanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.
- rosscomputerguy 6mo agoYeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix. I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.
- morphle 6mo agoYou can come work with us/for us and scale your SerDes design for us. That gets you actual wafer mask sets taped-out, a million chips and a WSI, not just test chips. A succesful SerDes will get you a job (at least in Europe). How fast will the SerDes run, 50 Mhz? It is not clear to me from the serdes_tile.dart source code. Can you share the verilog files?
- dizhn 6mo agoThere's also an open source Authenticator software with the same name.
- mosaibah 6mo ago[dead]
- logicchains 6mo agoHow far away are we from being able to run a hobby Linux on something like that, a completely hardware-backdoor-free system?
- morphle 6mo agoYou can already do that on several Risc-V chips with mmu.
- rosscomputerguy 6mo agoYou can already port over a RISC-V SoC to Aegis. I have not tested that yet but it is something I really want to do.
- fecal_henge 6mo agoHow do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
- lnsru 6mo agoThat’s a nice theory. Fab is one thing, but there are afterwards packaging and testing facilities where silicon can be swapped. I worked for a short time for a military contractor. They don’t X-ray every single chip. They just use it assuming the ordered chip is the one which was delivered by the markings on the package.
- jononor 6mo agoX-ray would be the traditional approach, though quite expensive. IRIS by bunnie is another approach that aims to bring cost way down. Ref https://www.bunniestudios.com/blog/2024/iris-infra-red-in-situ-project-updates/ https://www.bunniestudios.com/blog/2024/iris-infra-red-in-si...
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- smj-edison 6mo agoAs someone who has only dabbled with FPGAs before, this is incredible to see all the steps end-to-end for silicon development! I feel like the articles I've read always leave out details in one part or another, so it's interesting to see all the nix dependencies and build steps.
- morphle 6mo agoWe make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_MORPHLE_LOGIC.md https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale integrations (WSI) with 10 billion transistors at 180nm for $750. That yields around 300 million 'gates', the largest commercial FPGA's barely get to 3 million. So our Morphle Logic WSI is the largest and fastest (up to 12 Ghz) FPGA you could get if we can find a few hundred buyers who want to pay up front (crowdfunding). Please email me if you are interested in such a enormous fast FPGA. I'll buy an Aegis FPGFA test chip just to find out how hard it is to test a test chip. Good luck RossComputerGuy, I hope you get working chips back. The same fab and supplier lost our first taped-out chips in the mail... and then they went bankrupt.
- bgnn 6mo ago12 GHz on 180nm? Sorry, that's not possible. What's the actual clock speed?
- morphle 6mo agoMorphle Logic is asynchronous logic so there is no clock. At 110nm I measured when a transistor was switching the second transistor on its output. I can prove it, can you disprove it? A consistent 12Ghz signal cascade was (repeatedly) tested and confirmed on a 28nm asynchronous chip [1]. Why would it be impossible? [2]. We measure 800 Ghz and teraherz clocks on niobium superconducting Josephson Junctions [3,4,5]. [1] https://byrdsight.com/asynchronous-technology-has-its-time-finally-arrived/ https://byrdsight.com/asynchronous-technology-has-its-time-f... ( See also on the slides in the video talk) [2] "If an elderly but distinguished scientist says that something is possible, he is almost certainly right; but if he says that it is impossible, he is very probably wrong." - Arthur C. Clarke [3] Ivan Sutherland Keynote Single Flux Quantum SFQ Ditigal Electronics Digital circuits totally distinct from Quan https://www.youtube.com/watch?v=KMVV3ErGSVY https://www.youtube.com/watch?v=KMVV3ErGSVY [4] https://www.researchgate.net/profile/Jerome-Pety/publication/3120246_A_850-GHz_waveguide_receiver_employing_a_niobium_SIS_junctionfabricated_on_a_1-mm_Si3N4_membrane/links/0c9605253e9ead0393000000/A-850-GHz-waveguide-receiver-employing-a-niobium-SIS-junctionfabricated-on-a-1-mm-Si3N4-membrane.pdf https://www.researchgate.net/profile/Jerome-Pety/publication... [5] https://scholar.google.com/scholar?hl=en&as_sdt=0,5&qsp=3&q=900ghz+niobium&qst=bl https://scholar.google.com/scholar?hl=en&as_sdt=0,5&qsp=3&q=...
- jononor 6mo agoNice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
- rosscomputerguy 6mo agoYep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
- jononor 6mo agoWhat are your thoughts on including a RISC-V hardcore along with the gates? Because for almost all projects I can imagine using FPGA for, I would want a microcontroller also. This might however be slightly colored by me being a software/firmware first type of electronics engineer. Thinking especially for the smaller gate counts, like under 10k - because there a soft CPU takes up very precious resources.
- rosscomputerguy 6mo agoI've definitely had a thought about doing a hard core RISC-V SoC on a dev board.
- morphle 6mo ago1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.
- jononor 6mo agoInteresting! Which EDA tool must I use for those, and what is the price of that? Will these services accept a single run of 1k?
- Neywiny 6mo agoIs there a way in the DSP (that's the only one I looked at) to instead of going through a mux at the end just put the output flop optionally in a transparent mode if registering isn't enabled? I don't know if that's possible with the tooling but it seems like it'd save resources and reduce fanout.
- infinitewars 6mo agoThis is quite a milestone for open silicon. Having a completely auditable path from RTL down to GDS targeting the GF180MCU via wafer.space is no small feat-especially pulling it all together with a Nix-integrated toolchain and Dart for the hardware generation. On the I/O side, getting even a basic 400MHz oversampled SerDes into a first-gen test chip puts this way ahead of most academic open FPGA efforts. Really looking forward to seeing the Terra family expand and how the test chips perform.