rosscomputerguy

5 ms·

1. 1.▲
   Heimdall – config-driven RTL fuzzing harness for RISC-V on FPGA(github.com)

   2 points by rosscomputerguy 3mo ago|0 comments
2. 2.▲
   by rosscomputerguy 6mo ago

   Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11
3. 3.▲
   by rosscomputerguy 6mo ago

   Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11
4. 4.▲
   by rosscomputerguy 6mo ago

   I've definitely had a thought about doing a hard core RISC-V SoC on a dev board.
5. 5.▲
   by rosscomputerguy 6mo ago

   Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
6. 6.▲
   by rosscomputerguy 6mo ago

   You can already port over a RISC-V SoC to Aegis. I have not tested that yet but it is something I really want to do.
7. 7.▲
   by rosscomputerguy 6mo ago

   Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and
8. 8.▲
   by rosscomputerguy 6mo ago

   Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the
9. 9.▲
   Aegis – open-source FPGA silicon(github.com)

   153 points by rosscomputerguy 6mo ago|43 comments
10. 10.▲
    Ziptools – Modern zip and unzip replacements(github.com)

    2 points by rosscomputerguy 1y ago|0 comments
11. 11.▲
    SELinux on NixOS(tristanxr.com)

    16 points by rosscomputerguy 1y ago|2 comments