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GlobalFoundries to Acquire MIPS
- alephnerd 1y agoInteresting but complementary foray into owning the end-to-end pipeline of chip design, fabrication, and packaging - especially for embedded use cases. MIPS has also hitched it's horse to RISC-V now, and I am seeing a critical mass of talent and capital forming in that space.
- kragen 1y agoThe critical mass of talent and capital forming in the RISC-V space happened in 02019 at Alibaba: https://www.cnx-software.com/2019/07/27/alibaba-unveils-xuantie-910-16-core-risc-v-processor/ https://www.cnx-software.com/2019/07/27/alibaba-unveils-xuan... AFAIK MIPS still hasn't shipped a high-end processor competitive with the XuanTie 910 that article is about. And I think the billions of RISC-V microcontroller cores that have shipped already (10 billion as of 02022 according to https://wccftech.com/x86-arm-rival-risc-v-architecture-ships-10-billion-cores/ https://wccftech.com/x86-arm-rival-risc-v-architecture-ships...) are also mostly not from MIPS.
- garblegarble 1y agooff-topic but: I've noticed you prefix years with a zero in your HN comments. First I thought it was just a typo, but I see you've made several comments like that. Is there some significance, or are you just raising awareness of the year 9999 problem?
- deleted 1y ago[deleted]
- rrakow 1y agoI think that's some "Long Now Foundation" meme.
- dcminter 1y agoThat. Personally I think it's performative nonsense, but you have to admire the commitment to it.
- kstrauser 1y agoI suspect it’s counterproductive, though, like deliberately not using pronouns and always referring to someone by name. The intent might be to draw attention to the author’s cause, but it’s more likely to come across that the author just writes weirdly.
- dcminter 1y agoEh, I also think it's harmless, and lends a certain "brand" to their posts - which are usually quite good otherwise. Better to be weird than dull, right?
- kstrauser 1y agoI guess, unless the offputting:goodness ratio gets lopsided and makes people start ignoring them. Frankly, something about that leading 0 makes me grit my teeth and stop reading. I can't explain why it affects me like that. Perhaps I'm the only one who does, although threads like this seem to pop up whenever they post so I don't think so. If HN had a mute button, I'd probably use it just because it annoys me to that level. Edit: And now that we're talking about it, they seem to have the need to mention a specific year way more than most, as though deliberately looking for opportunities to draw attention to themselves. Oof. That just made it about 10x more grating to me.
- dcminter 1y agoI do get where you're coming from; for me I think it interrupts the way I scan text - a date would be unconsciously absorbed but these stand out as abnormal artefacts requiring full attention.
- acdha 1y agoIt’s the Long Now Foundation’s convention - a bit cultish but harmless. https://longnow.org/ideas/long-now-years-five-digit-dates-and-10k-compliance-at-home/ https://longnow.org/ideas/long-now-years-five-digit-dates-an...
- nine_k 1y ago(BTW why do you write years with a leafing zero? Do you expect these post to still matter past year 9999?)
- dcminter 1y ago...and if he does, why does he then consider the year 99999 to be out of reach? As I understand it the idea is to promote "long term thinking" but I really don't see how this affectation is actually supposed to achieve anything beyond mildly irritating/confusing the reader. At least the Long Now Foundation stuff comes with that context built-in. https://longnow.org/ https://longnow.org/
- ndiddy 1y agoGood point, I will start the Longer Now foundation and start adding two zeroes to the front of all my years.
- hypercube33 1y agoThis whole line of conversation and use of the leading zero reminds me of The Church of MOO from the old internet.
- dcminter 1y agoHuh, I know about Bob Dobson et al, but MOO-ism somehow escaped my notice back in the day. http://textfiles.com/occult/MOOISM/ http://textfiles.com/occult/MOOISM/ I have some retro-reading to do.
- hulitu 1y ago> AFAIK MIPS still hasn't shipped a high-end processor competitive with the XuanTie 910 that article is about The last high end MIPS was in the SGI times, 30 years ago.
- kragen 1y agoYes, but their claims over the last few years have been that their RISC-V implementations will be super fast, not like all those pikers, because they're using MIPS microarchitectural techniques. And so far I haven't seen them ship anything that substantiates that.
- chasil 1y agoLoongson was making them until recently. https://www.theregister.com/2025/05/06/loongson_inspur_cloudos/ https://www.theregister.com/2025/05/06/loongson_inspur_cloud...
- kragen 1y agoYes, but MIPS wasn't.
- Findecanor 1y agoIt was some time ago that MIPS did announce that they had competitive RISC-V cores and had signed customers for them: LG and in the automotive sector. I'd think those should be taped out by now, but who knows... I think the C910 looks better on paper than it performs in practice. I hope that isn't the case for MIPS.
- kragen 1y agoDo you have any details?
- Findecanor 1y agoI can only refer to MIPS' own press releases, unfortunately. They mention 4-wide OoO, RV64GH + Zbb + Zba. no V. That is a frustrating pattern in the RISC-V world. Many companies that boast having x wide cores with y SPECint numbers but nothing that has been independently verified.
- kragen 1y agoNo V sounds like a bad sign for performance. Do they have any part numbers?
- monocasa 1y agoAdding to what was said, it also suspiciously looks like a MIPS core with a RISC-V frontend strapped to it sort of like Qualcomm did with their Nuvia AArch64 core. Particularly stuff like the soft fill TLB from m-mode looks just like MIPS coprocessor 0.
- ajb 1y agoThere's nothing especially wrong with using an existing backend design and transitioning it to another ISA; a number of teams did that from mips->arm and had success with the result. Of course, if you ship too early you may be missing some features.
- ajb 1y agoIt's an interesting comparison because MIPS used to occupy the niche that RV does now - an ISA that anyone could implement. Lots of companies had their own mips implementation, but still might use an implementation from mips-the-company because even if you have your own team, you probably don't want to implement every core size that you might need. But then for some reason lots of them switched to using ARM, within a few years (in some cases getting an architecture licence and keeping their CPU team). It seems like RV has a more stable structure, as the foundation doesn't licence cores, so even if one or two of the implementors die it won't necessarily reflect on the viability of the ecosystem
- bobmcnamara 1y ago> an ISA that anyone could implement. You want to burn your initial capital on lawyers? This is MIPS we're talking about.
- somanyphotons 1y agoSuddenly another company that has (old?) fabs and a cpu design team in-house This could be interesting to see how much they try to loss-lead to get market share in the low-end
- deleted 1y ago[deleted]
- kragen 1y agoGF's fabs aren't that old. They were neck-and-neck with TSMC until 02018, when they could do 12nm: https://web.archive.org/web/20190107061855/https://www.v3.co.uk/v3-uk/news/3061809/globalfoundries-drops-7nm-as-amd-goes-to-tsmc-instead https://web.archive.org/web/20190107061855/https://www.v3.co...
- kasabali 1y agoImagine canning your 7nm process last minute only few years before the chip shortage. Must be the most moronic decision ever. and it's not like 20/20 hindsight either, because every hardware enthusiast knew at the time Intel was having troubles and was worried TSMC (and Samsung at the time) were going to be the only fabs producing leading edge lithographies.
- bee_rider 1y agoI think it would require some work to call it a “moronic decision.” My suspicion is that even if they could see the future and predict that shortage, 7nm by 2020/2021 was not on the table for them. These nm values are really bullshit anyway, but the tech node that was supposed to be Intel’s 7nm, which ended up being called “Intel 4” (because they branded some 10nm tech as Intel 7), only came out in like 2023. Given they Global Foundries was always behind Intel, suddenly leapfrogging them by 2-3 years would be quite a feat.
- kasabali 1y agoOh no, it is a moronic decision and everyone thought so even then. It was a competitive process, they said volume production was due in late 2018 and they canned it at the very last minute citing it financially not feasible. You can read details at this news article (https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development https://www.anandtech.com/show/13277/globalfoundries-stops-a...) or thousands of forum discussions regarding the news. No need to even look that far, just skimp the discussions on the forum topic below the news article I linked and it was plain as a day to anyone what would happen. > These nm values are really bullshit anyway, but the tech node that was supposed to be Intel’s 7nm, which ended up being called “Intel 4” (because they branded some 10nm tech as Intel 7), only came out in like 2023. Given they Global Foundries was always behind Intel, suddenly leapfrogging them by 2-3 years would be quite a feat. This is a very weak argument. Intel was ahead of everyone, now everyone is ahead of Intel. Remember TSMC's blunder processes like 20nm? How they turned around after that? Or how GloFo has had always mediocre processes but they finally hit the nail in the head with their 14/12nm? Fab business has always had companies leapfrogging each other, it turns out the worst sin is not trying. GloFo's greedy investors chose to bury the business in the ground for their short term profits.
- somanyphotons 1y agoHow are the various riscv cpu IP vendors generally doing financially? Is this the very beginning of a market consolidation?
- kragen 1y agoI don't think people generally pay for RISC-V CPU IP.
- somanyphotons 1y agoSure they do, most IP is proprietary
- MisterTea 1y agoThey do if they aren't implementing the ISA in silicon themselves. Its interesting to see who's designs are selling, who's aren't and why.
- Keyframe 1y agoFor ISA? Certainly not. For actual designs, for sure. Why wouldn't they unless there's some open source designs they'd be using?
- kragen 1y agoWell, because there are open-source designs they'd be using. The GD32V microcontroller, for example, uses Nucleisys's BumbleBee, and high-performance chips from several vendors use Brother Honey Badger's Apache-licensed XuanTie C910: https://github.com/XUANTIE-RV/openc910 https://github.com/XUANTIE-RV/openc910 But see https://news.ycombinator.com/item?id=44503847 https://news.ycombinator.com/item?id=44503847
- ryao 1y agoThere are open source designs. Here is one: https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom
- aseipp 1y ago
- sloemoe 1y agoPut that in your delay slot and smoke it. https://en.wikipedia.org/wiki/Delay_slot https://en.wikipedia.org/wiki/Delay_slot I'm surprised by how many other architectures use it.
- burnt-resistor 1y agoSPIM says "all shall be efficient single cycle instructions and to heck with the MHz wars!" /s
- jnwatson 1y agoThe TI C40 used them.
- kragen 1y agoIt seemed like a good idea in 01981; the purported expansion of MIPS was "Microprocessor without Interlocked Pipeline Stages", although of course it's a pun on "millions of instructions per second". By just omitting the interlock logic necessary to detect branch hazards and putting the responsibility on the compiler, you get a chip that can run faster with less transistors. IBM's 45000-transistor 32-bit RISC "ROMP" was fabbed for use in IBM products that year, which gives you an idea of how precious silicon area was at the time. Stanford MIPS was extremely influential, which was undoubtedly a major factor in many RISC architectures copying the delay-slot feature, including SPARC, the PA-RISC, and the i860. But the delay slot really only simplifies a particular narrow range of microarchitectures, those with almost exactly the same pipeline structure as the original. If you want to lengthen the pipeline, either you have to add the interlocks back in, or you have to add extra delay slots, breaking binary compatibility. So delay slots fell out of favor fairly quickly in the 80s. Maybe they were never a good tradeoff. One of the main things pushing people to RISC in the 80s was virtual memory, specifically, the necessity of being able to restart a faulted instruction after a page fault. (See Mashey's masterful explanation of why this doomed the VAX in https://yarchive.net/comp/vax.html https://yarchive.net/comp/vax.html.) RISC architectures generally didn't have multiple memory accesses or multiple writes per instruction (ARM being a notable exception), so all the information you needed to restart the failed instruction successfully was in the saved program counter. But delay slots pose a problem here! Suppose the faulting instruction is the delay-slot instruction following a branch. The next instruction to execute after resuming that one could either be the instruction that was branched to, or the instruction at the address after the delay-slot instruction, depending on whether the branch was taken or not. That means you need to either take the fault before the branch, or the fault handler needs to save at least the branch-taken bit. I've never programmed a page-fault handler for MIPS, the SPARC, PA-RISC, or the i860, so I don't know how they handle this, but it seems like it implies extra implementation complexity of precisely the kind Hennessy was trying to weasel out of. The WP page also mentions that MIPS had load delay slots, where the datum you loaded wasn't available in the very next instruction. I'm reminded that the Tera MTA actually had a variable number of load delay slots, specified in a field in the load instruction, to allow the compiler to allow as many instructions as it could for the memory reference to come back from RAM over the packet-switching network. (The CPU would then stall your thread if the load took longer than the allotted number of instructions, but the idea was that a compiler that prefetched enough stuff into your thread's huge register set could make such stalls very rare.)
- musicale 1y agoMIPS seems like a story of missed (mipsed?) opportunities. If MIPS had really been (or remained) an open architecture, there would have been little need for RISC-V. They had a decade+ head start in terms of tool support and silicon implementation, compressed/16-bit instruction formats, full 64-bit instruction sets, and scaling from embedded systems to HPC.
- bobmcnamara 1y agoThat whacky multiplier setup though. Who could've ever foreseen that bottleneck.
- stevefan1999 1y agoAMD's former girlfriend now married MIPS. Yikes