7 ms·

Intel Brings Chiplets to Data Center CPUs

49 points by craigjb 5y ago

OrvalWintermute 5y ago
I thought AMD had already brought chiplets to data center CPUs a long time ago [1], [2] and that is why they are leading currently, now that they have multiple generations of chiplet data center CPUs out? [3] [1] https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/ https://www.wired.com/story/keep-pace-moores-law-chipmakers-... [2] https://www.tomshardware.com/news/amd-epyc-processor-models-pricing,34833.html https://www.tomshardware.com/news/amd-epyc-processor-models-... [3] https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/ https://www.wired.com/story/keep-pace-moores-law-chipmakers-...
- throwawaylinux 5y ago
  You are right AMD has done that. I don't know if it is the reason they are leading -- they have better process technology and in many ways better core design as well. But this story is about Intel. Though it depends on how you define "chiplet". In this article it looks like 4 identical chips wired on a package each with their own IO and memory controllers. That's very different from from AMD's core chips wired to an IO chip, and is nothing new for Intel. https://en.wikipedia.org/wiki/Multi-chip_module https://en.wikipedia.org/wiki/Multi-chip_module It's the expected response from Intel when they are unable to compete on throughput per socket with a single chip (they went to DCMs during the period of Opteron dominance too). I don't know what the story is really -- they said the latency was too high to do this before but they've already done something effectively the same (and multi socket SMP systems have even higher chip to chip latency again, so clearly it can be done). I guess they just improved the on package interconnect performance a bit, but almost certainly they would have done a multi chip to compete with AMD even if they were not able to improve that latency.
  - wmf 5y ago
    Sapphire Rapids is more similar to AMD's "Naples" Epyc from 2017 which also used four identical dies. Intel's mesh and EMIB should give Sapphire Rapids dramatically more internal bandwidth than AMD designs. It counts as chiplets IMO because the dies aren't intended to be used standalone.
    - throwawaylinux 5y ago
      More similar to that than? The current AMD chip+io die approach? Sure. As I said, "chiplet" just depends on a definition, there is really no good single one. Almost certainly the dies could be used standalone, and it wouldn't be surprising if some were for low end SKUs (modulo the statement in the article that they won't for this generation) -- there are some mesh IOs on some length about 1/2 the die on two edges, that's it. Not much area.
- icegreentea2 5y ago
  Yes. The article (second paragraph) clearly states that this is a first for Intel, not for Data Centers. Given that this is a trade-ish publication, I think writers/editors will more or less assume their audience understands the smackdown that AMD has been laying on Intel and AMD's chiplet strategy.
  - Dylan16807 5y ago
    Though it's not even really a first for Intel. They made the Xeon 9200 series two years ago, and while those were slapdash and hard to buy, it's hard to argue that they don't deserve this crown. Two dies in a single package, each with 28 cores and memory controllers and I/O. Even when Intel moves to heterogeneous dies, that won't actually be a first for them, even in the modern era. Several early i3/i5/i7 models had one die with two cores and another die that handled memory and I/O.
    - TazeTSchnitzel 5y ago
      The 9200 was a reaction to AMD's EPYC so surely AMD gets the crown?
      - 656565656565 5y ago
        How long have IBM been doing MCM ?
        baybal2 5y ago
        Like 50 years?
      - Dylan16807 5y ago
        The crown of "first for Intel" My comment started with that phrase because that's what it was about, but I guess the wording confused people?
- systemvoltage 5y ago
  Chiplets aren’t a desired technology. It’s done for either yield (more common) or thermal reasons (less common). It’s not something to brag about.
  - justincormack 5y ago
    also done to allow more SKUs from the same components, allowing AMD to make up any mix of 8 to 64 core chips without manufacturing fixed quantities of each or disabling most of the die (expensive)
  - wmf 5y ago
    There's some truth to this in the sense that a single die would almost always have better performance than chiplets, but chiplets also reduce cost and they make larger core counts possible. A single die literally can't fit more than ~48 big cores with the associated cache and I/O, so 56, 64, or 96-core processors are only possible using chiplets.
    - systemvoltage 5y ago
      That was indeed my point - you said it perfectly. I meant, that there is nothing for the customer in chiplets except cost. Intel went the EMIB route to route through embedded silicon but people need to be reminded on HN that chiplet/fabric architecture is not something to brag about as a feature - which is what a lot of comments are doing (AMD did it first!). Intel went through this mess because they had to due to yield. It ain't a feature for the customer.
- philjohn 5y ago
  Not only that, but Intel slides ridiculed AMD "glueing" cores together. https://www.pcgamer.com/uk/intel-slide-criticizes-amd-for-using-glued-together-dies-in-epyc-processors/ https://www.pcgamer.com/uk/intel-slide-criticizes-amd-for-us...
shadilay 5y ago
I wonder if they'll call it "glued-together". https://www.pcgamer.com/intel-slide-criticizes-amd-for-using-glued-together-dies-in-epyc-processors/ https://www.pcgamer.com/intel-slide-criticizes-amd-for-using... The 4 die SoC does look an awful lot like 1st gen EPYC.
- mappu 5y ago
  It's especially ironic because Intel had also previously "glued together" chiplets for the C2Qs and their equivalent Xeons (e.g. X3200 series). > The 2 × 2 "quad-core" (dual-die dual-core[17]) comprised two separate dual-core die next to each other in one CPU package.
  - h2odragon 5y ago
    https://en.wikipedia.org/wiki/Pentium_Pro https://en.wikipedia.org/wiki/Pentium_Pro
    - lostmsu 5y ago
      > Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion floating point operations per second (teraFLOPS) performance mark. Amazing. RTX 3090 has peak fp32 performance of 35 TFLOPS.
      - wtallis 5y ago
        I believe that almost all floating point instructions on the Pentium Pro had the same performance whether you were using the x87 FPU in 32-bit, 64-bit or 80-bit mode, so it's probably more fair to compare ASCI Red against the fp64 performance of today's GPUs. NVIDIA usually doesn't let the consumer GeForce parts get anywhere near 1 TFLOPS for double-precision. You have to look at some of their Titan or datacenter GPUs to get that kind of double-precision performance.
  - tedunangst 5y ago
DSingularity 5y ago
Intel is in the cusp of getting taking out. Architectures and process technologies are both multiple generations behind. AMD has 10x its server share. If the trend sustains for one more generation the majority of the market will go to AMD.
- Hikikomori 5y ago
  10x? Where did you find those numbers.
  - DSingularity 5y ago
    I actually meant 10x growth in its share of server CPU sells over past 5 years. They went from 1% of the market to roughly 10%.
- throwawaylinux 5y ago
  Not that Intel is in a good spot, but Intel for about the past 4 years has been in the position that AMD (and TSMC) had been in for much of the past 30 years (with some brief switches). Actually it's not even that in the case of Intel vs AMD because Intel continues to have large revenues and profits (gross margins slipped from usual low-60s to low-50s in the past few years). Whereas AMD was really struggling as a company for long periods. Could Intel be in terminal decline as a CPU design and/or silicon manufacturing leader? It's possible. Is it a done deal or are they "finished" any time soon? No way. It will be many years while this plays out.
  - totalZero 5y ago
    Intel is nowhere close to the doldrums of yesteryear's AMD. It continues to command the lion's share of the x86 market, and hasn't needed to sell off assets in order to remain afloat. In fact, Intel's business has never been better. The AMD-favoring narrative that the firms have flip-flopped is not backed up by market share research, nor corroborated by quarterly filings.
    - 5y ago
jagger27 5y ago
I find it interesting that the dies aren’t completely identical like Zen chiplets are. If I am reading the diagram correctly, it looks like the tiles diagonal from each other are the same. Kind of neat that they’ll have left-hand and right-hand wafers.
- Dylan16807 5y ago
  I wouldn't read too much into such a simple diagram. Early on a lot of people thought Epyc had mirrored dies but they're actually all the same.
  - dogma1138 5y ago
    Sapphire Rapids is confirmed to have mirrored dies, it’s not just a block diagram. This is to make routing easier on packaging as well as optimize motherboard layout when it comes to memory, power and IO.
chx 5y ago
> Intel Corp.’s fourth-generation Xeon processor, codenamed Sapphire Rapids If you are just as confused as I am at "fourth generation" when Xeon has been around for decades, they mean "fourth-generation Xeon Scalable Processor (SP)". Skylake-SP, Cascade Lake-SP, Ice Lake-SP were the previous generations. Where Xeon processors previously used E3/E5/E7 designations for 1/2/4+ socket capabilities, SP CPUs use metallic prefixes: Bronze representing basic processors, Silver low power, Gold adding different options for advanced interconnects and integrated accelerators, and Platinum offering the widest range of capabilities.
LargoLasskhyfv 5y ago
They must be high on fumes of glue!

49 points by craigjb 5y ago

I thought AMD had already brought chiplets to data center CPUs a long time ago [1], [2] and that is why they are leading currently, now that they have multiple generations of chiplet data center CPUs out? [3] [1] https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/ https://www.wired.com/story/keep-pace-moores-law-chipmakers-... [2] https://www.tomshardware.com/news/amd-epyc-processor-models-pricing,34833.html https://www.tomshardware.com/news/amd-epyc-processor-models-... [3] https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/ https://www.wired.com/story/keep-pace-moores-law-chipmakers-...

throwawaylinux 5y ago
You are right AMD has done that. I don't know if it is the reason they are leading -- they have better process technology and in many ways better core design as well. But this story is about Intel. Though it depends on how you define "chiplet". In this article it looks like 4 identical chips wired on a package each with their own IO and memory controllers. That's very different from from AMD's core chips wired to an IO chip, and is nothing new for Intel. https://en.wikipedia.org/wiki/Multi-chip_module https://en.wikipedia.org/wiki/Multi-chip_module It's the expected response from Intel when they are unable to compete on throughput per socket with a single chip (they went to DCMs during the period of Opteron dominance too). I don't know what the story is really -- they said the latency was too high to do this before but they've already done something effectively the same (and multi socket SMP systems have even higher chip to chip latency again, so clearly it can be done). I guess they just improved the on package interconnect performance a bit, but almost certainly they would have done a multi chip to compete with AMD even if they were not able to improve that latency.
- wmf 5y ago
  Sapphire Rapids is more similar to AMD's "Naples" Epyc from 2017 which also used four identical dies. Intel's mesh and EMIB should give Sapphire Rapids dramatically more internal bandwidth than AMD designs. It counts as chiplets IMO because the dies aren't intended to be used standalone.
  - throwawaylinux 5y ago
    More similar to that than? The current AMD chip+io die approach? Sure. As I said, "chiplet" just depends on a definition, there is really no good single one. Almost certainly the dies could be used standalone, and it wouldn't be surprising if some were for low end SKUs (modulo the statement in the article that they won't for this generation) -- there are some mesh IOs on some length about 1/2 the die on two edges, that's it. Not much area.
icegreentea2 5y ago
Yes. The article (second paragraph) clearly states that this is a first for Intel, not for Data Centers. Given that this is a trade-ish publication, I think writers/editors will more or less assume their audience understands the smackdown that AMD has been laying on Intel and AMD's chiplet strategy.
- Dylan16807 5y ago
  Though it's not even really a first for Intel. They made the Xeon 9200 series two years ago, and while those were slapdash and hard to buy, it's hard to argue that they don't deserve this crown. Two dies in a single package, each with 28 cores and memory controllers and I/O. Even when Intel moves to heterogeneous dies, that won't actually be a first for them, even in the modern era. Several early i3/i5/i7 models had one die with two cores and another die that handled memory and I/O.
  - TazeTSchnitzel 5y ago
    The 9200 was a reaction to AMD's EPYC so surely AMD gets the crown?
    - 656565656565 5y ago
      How long have IBM been doing MCM ?
      - baybal2 5y ago
        Like 50 years?
    - Dylan16807 5y ago
      The crown of "first for Intel" My comment started with that phrase because that's what it was about, but I guess the wording confused people?
systemvoltage 5y ago
Chiplets aren’t a desired technology. It’s done for either yield (more common) or thermal reasons (less common). It’s not something to brag about.
- justincormack 5y ago
  also done to allow more SKUs from the same components, allowing AMD to make up any mix of 8 to 64 core chips without manufacturing fixed quantities of each or disabling most of the die (expensive)
- wmf 5y ago
  There's some truth to this in the sense that a single die would almost always have better performance than chiplets, but chiplets also reduce cost and they make larger core counts possible. A single die literally can't fit more than ~48 big cores with the associated cache and I/O, so 56, 64, or 96-core processors are only possible using chiplets.
  - systemvoltage 5y ago
    That was indeed my point - you said it perfectly. I meant, that there is nothing for the customer in chiplets except cost. Intel went the EMIB route to route through embedded silicon but people need to be reminded on HN that chiplet/fabric architecture is not something to brag about as a feature - which is what a lot of comments are doing (AMD did it first!). Intel went through this mess because they had to due to yield. It ain't a feature for the customer.
philjohn 5y ago
Not only that, but Intel slides ridiculed AMD "glueing" cores together. https://www.pcgamer.com/uk/intel-slide-criticizes-amd-for-using-glued-together-dies-in-epyc-processors/ https://www.pcgamer.com/uk/intel-slide-criticizes-amd-for-us...

shadilay 5y ago

I wonder if they'll call it "glued-together". https://www.pcgamer.com/intel-slide-criticizes-amd-for-using-glued-together-dies-in-epyc-processors/ https://www.pcgamer.com/intel-slide-criticizes-amd-for-using... The 4 die SoC does look an awful lot like 1st gen EPYC.

mappu 5y ago
It's especially ironic because Intel had also previously "glued together" chiplets for the C2Qs and their equivalent Xeons (e.g. X3200 series). > The 2 × 2 "quad-core" (dual-die dual-core[17]) comprised two separate dual-core die next to each other in one CPU package.
- h2odragon 5y ago
  https://en.wikipedia.org/wiki/Pentium_Pro https://en.wikipedia.org/wiki/Pentium_Pro
  - lostmsu 5y ago
    > Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion floating point operations per second (teraFLOPS) performance mark. Amazing. RTX 3090 has peak fp32 performance of 35 TFLOPS.
    - wtallis 5y ago
      I believe that almost all floating point instructions on the Pentium Pro had the same performance whether you were using the x87 FPU in 32-bit, 64-bit or 80-bit mode, so it's probably more fair to compare ASCI Red against the fp64 performance of today's GPUs. NVIDIA usually doesn't let the consumer GeForce parts get anywhere near 1 TFLOPS for double-precision. You have to look at some of their Titan or datacenter GPUs to get that kind of double-precision performance.
- tedunangst 5y ago

DSingularity 5y ago

Intel is in the cusp of getting taking out. Architectures and process technologies are both multiple generations behind. AMD has 10x its server share. If the trend sustains for one more generation the majority of the market will go to AMD.

Hikikomori 5y ago
10x? Where did you find those numbers.
- DSingularity 5y ago
  I actually meant 10x growth in its share of server CPU sells over past 5 years. They went from 1% of the market to roughly 10%.
throwawaylinux 5y ago
Not that Intel is in a good spot, but Intel for about the past 4 years has been in the position that AMD (and TSMC) had been in for much of the past 30 years (with some brief switches). Actually it's not even that in the case of Intel vs AMD because Intel continues to have large revenues and profits (gross margins slipped from usual low-60s to low-50s in the past few years). Whereas AMD was really struggling as a company for long periods. Could Intel be in terminal decline as a CPU design and/or silicon manufacturing leader? It's possible. Is it a done deal or are they "finished" any time soon? No way. It will be many years while this plays out.
- totalZero 5y ago
  Intel is nowhere close to the doldrums of yesteryear's AMD. It continues to command the lion's share of the x86 market, and hasn't needed to sell off assets in order to remain afloat. In fact, Intel's business has never been better. The AMD-favoring narrative that the firms have flip-flopped is not backed up by market share research, nor corroborated by quarterly filings.
  - 5y ago

jagger27 5y ago

I find it interesting that the dies aren’t completely identical like Zen chiplets are. If I am reading the diagram correctly, it looks like the tiles diagonal from each other are the same. Kind of neat that they’ll have left-hand and right-hand wafers.

Dylan16807 5y ago
I wouldn't read too much into such a simple diagram. Early on a lot of people thought Epyc had mirrored dies but they're actually all the same.
- dogma1138 5y ago
  Sapphire Rapids is confirmed to have mirrored dies, it’s not just a block diagram. This is to make routing easier on packaging as well as optimize motherboard layout when it comes to memory, power and IO.

chx 5y ago

> Intel Corp.’s fourth-generation Xeon processor, codenamed Sapphire Rapids If you are just as confused as I am at "fourth generation" when Xeon has been around for decades, they mean "fourth-generation Xeon Scalable Processor (SP)". Skylake-SP, Cascade Lake-SP, Ice Lake-SP were the previous generations. Where Xeon processors previously used E3/E5/E7 designations for 1/2/4+ socket capabilities, SP CPUs use metallic prefixes: Bronze representing basic processors, Silver low power, Gold adding different options for advanced interconnects and integrated accelerators, and Platinum offering the widest range of capabilities.

LargoLasskhyfv 5y ago

They must be high on fumes of glue!