e7h4nz

5 ms·

1.
Yet Another AI Teammate(yaat.sh)
2 points by e7h4nz 4mo ago|0 comments
2.
Ts-rest – what happens when a 3.3k star OSS project goes dormant
1 points by e7h4nz 5mo ago|0 comments
3.
by e7h4nz 5mo ago
We had a similar journey with Neon's branching. Initially it was a huge win for our CI workflows — spinning up an isolated, production-shaped database per PR made migration testing and integration checks dramatically more realistic tha
4.
by e7h4nz 5mo ago
If AI agents can proficiently use whatsapp I would assume that two-thirds of the people chatting with me in my contacts are actually just bots messaging me.
5.
by e7h4nz 6mo ago
In this problem domain, I believe humanity is still in a very early stage. What we can do is treat the agent and its operating environment as a "black box" and audit all incoming and outgoing network request traffic. This approach
6.
by e7h4nz 6mo ago
Did you actually read this article or try to understand what OneCLI does?
7.
by e7h4nz 6mo ago
Removed microservices and RPC, keep all TypeScript codes in a single monorepo. Avoiding `any` and using ts-rest automatically keep types synchronized between the web and frontend applications. This has made my life much easier.
8.
by e7h4nz 6mo ago
I worked on a core Spring Boot project for five or six years at a very large enterprise. In my opinion, the most dangerous thing about this framework is that it makes its core users feel far too self-assured. When looking at problems, your
9.
by e7h4nz 6mo ago
Agreed. we hit some wired case on Adreno 530, ran into bizarre GPU instruction set issues with the compute shader compressor, that only manifested on Adreno 53x. Ended up having to add a device detection path, and fall back to CPU compressi
10.
by e7h4nz 6mo ago
I really resonated with the end of README.md. I have a huge stack of embedded development boards at home—all kinds of SBCs, microcontrollers, FPGAs, and more. Over the years, as a hobbyist, I've bought them consistently. Overall, I’ve
11.
by e7h4nz 6mo ago
On a practical level, you're right, most of my team's work is done in Verilog. That being said, I still have a preference for the VHDL simulation model. A design that builds correctness directly into the language structure is inhe
12.
by e7h4nz 6mo ago
The irony of hardware image compression is that the devices that need it most are typically older, bandwidth-constrained SoCs. However, these are precisely the devices that do not support modern formats. Technologies like ARM AFRC and PVRIC
13.
by e7h4nz 6mo ago
The Delta Cycle logic is actually quite similar to functional reactive programming. It separates how a value changes from when a process responds to that change. VHDL had this figured out as early as 1987. I spent many years writing Verilog
14.
by e7h4nz 8mo ago
hi, I'm VM0's developer. Happy to answer your questions. I fully agree, without clear architecture docs, I wouldn't trust an infra service either. We're working on technical documentation now. Here is some quick summaris