claudio_mos

8 ms·

1.
by claudio_mos 6mo ago
> The first question has to be: why? There are many reasons. The main one is that no architecture exists that models such a complex ternary processor. At most, there are "on paper" implementations of much less complex architect
2.
by claudio_mos 6mo ago
I'm the author. The 5500FP is a complete 24-trit balanced ternary RISC processor implemented on an Efinix Trion T20F256 FPGA, with a custom open hardware development board (GargantuRAM). The ISA is fully documented, including instruc
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Show HN: I designed a 24-trit balanced ternary RISC processor on FPGA(zenodo.org)
1 points by claudio_mos 6mo ago|3 comments
4.
by claudio_mos 2y ago
I have updated the site with a references section. Here you will find some links to recent studies on native ternary semiconductors.
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by claudio_mos 2y ago
Oh, I don't think at all that this method of operation (Tomasulo?) is remotely close to a real dataflow in terms of efficiency and complexity. But as I wrote, dataflow is another story ;)
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by claudio_mos 2y ago
ok, now i can say for sure, you didn't read the site well at all. you didn't even read my answers well. maybe you would have understood that now mosfet level design is already happening but it only concerns the CPU (if you want to
7.
by claudio_mos 2y ago
Thanks! Ternary data is definitely more efficient than binary, regardless of your use, not just for AI. I honestly don't know if it's faster, can you give me information on where you read that? I imagine it's possible even if
8.
by claudio_mos 2y ago
Just as simple: it's easy to have positive voltage, negative voltage or no voltage ;) Thanks for the help, maybe we need someone to write the basic software right now!
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by claudio_mos 2y ago
Ok, maybe that's not clear, probably my not-so-perfect English is a problem. The dataflow architecture was the initial idea. What I'm talking about now is the ternary processor, a normal VonNeumann processor with ternary data and
10.
by claudio_mos 2y ago
Yes, the serial buffer is included in the motherboard. The problem is not so much for OUT but for IN, if the buffer fills up. As for the bus addresses, the counter program starts from the lowest address. The mainboard obviously knows how mu
11.
by claudio_mos 2y ago
Yes, of course to load a character I use LD.T Uhmm..actually the OUT instruction ends immediately after its normal cycle. the character is sent to the mainboard that reads it and puts it in a buffer and passes from a buffer. (it's more
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by claudio_mos 2y ago
Thanks! We sold about 30 CPUs of the old version, then we had to stop because the main component was not available for years, right after the pandemic. Now we use an alternative component that is also less expensive and we have added severa
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by claudio_mos 2y ago
Thanks! Of course it can't be binary, but it reads purely ternary electrical signals. You can see an example of the assembly in one of the figures on the web page (even if it's an old listing). Expect all the normal operations a b
14.
by claudio_mos 2y ago
We do not currently have any integrated circuits, all the circuits (and PCBs) are entirely designed by me. What I said is that we are using a manufacturing process to do the VLSI layout to integrate everything into a single component, but c
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by claudio_mos 2y ago
Thanks!
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by claudio_mos 2y ago
Thanks!
17.
by claudio_mos 2y ago
That code in the figure is an old code, honestly it's an old screenshot that I don't even remember what it corresponds to, but your analysis is basically correct, even though I used absolute addresses before while now everything i
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by claudio_mos 2y ago
Interesting! I am not familiar with how integer weights work for LLMs, can you give me more details?
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Show HN: Ternary Computer System(ternary-computing.com)
145 points by claudio_mos 2y ago|40 comments