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Show HN: Ternary Computer System
Hi everyone!
I'm an Italian programmer, very passionate about computer architecture. Some time ago I realized that some architectures potentially much superior to the classic VonNeumann, have been forgotten because there were no reliable technical solutions to implement them.
One of these architectures particularly struck me and it is the "Dataflow architecture", in which there is no Program counter, but the instructions are executed in real contemporaneity whenever the operands are available.
In trying to find a technical solution that implements this type of architecture effectively (spoiler: yes, maybe I succeeded but I still have to test the real correct functioning!) I realized that this solution works more than well with three logical states. And at this point I discovered that perhaps it is better to implement a CPU with three states (ternary) instead of a white one. This as a first step to realize my dataflow solution.
Obviously a world has opened up to me regarding ternary CPUs, I have discovered not only that they are the best solution implemented for a computing device, but also that an increasing number of university and researcher papers are dealing with them in recent times.
This is also thanks to the enormous potential compared to normal CPUs; lower circuit complexity (and also lower consumption and lower heat production) but at the same time the truly formidable information representation capabilities compared to binary counterparts!
So here I am creating this ternary CPU and all the hardware and software to be able to use it immediately. In the link you have found some other details, but obviously for questions, suggestions or anything else you can insert your comment here!
- lawls 2y agoThis is something I'm convinced we need for integer weights in LLMs.
- claudio_mos 2y agoInteresting! I am not familiar with how integer weights work for LLMs, can you give me more details?
- eightysixfour 2y agoThis is what is being referenced: https://arxiv.org/html/2410.16144v2 https://arxiv.org/html/2410.16144v2
- claudio_mos 2y agoThanks!
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- AlotOfReading 2y agoVery cool to see that you've achieved a hardware prototype. Looks great. If you're more interested in exploring your ideas about ternary dataflow computing, is there a reason you didn't start with an FPGA instead? The gap between idea and prototype is much smaller and there's even dataflow DSLs like Tapa if you don't want to write the HDL: https://github.com/rapidstream-org/rapidstream-tapa https://github.com/rapidstream-org/rapidstream-tapa
- claudio_mos 2y agoThanks!
- wd776g5 2y agoThis is an interesting project. Two questions: one, are you selling something? Can I buy a dev board? Can I look at your operating system? Or is this all closed source? If it's closed that's OK just wondering. Second question, what do the logic gates look like in a ternary system? Is there a list of them somewhere?
- claudio_mos 2y agoThanks! We sold about 30 CPUs of the old version, then we had to stop because the main component was not available for years, right after the pandemic. Now we use an alternative component that is also less expensive and we have added several new features. The current development board is not fully functional, we are working on ETH, RTC and also fixing a few other things. We expect it to be fully functional and available by April 2025. The OS is actually just very simple; it boots an image from SD, sets up the interrupt table, initializes a list of free memory and that's it for now. This part will be OpenSource so that we can take inspiration to make something better. The development board (mainboard) will also be open hardware and should be listed on GitHub. The macro assembler is freeware, but only because (currently) the code is really a bit messy! For ternary logic functions you can refer to this site that inspired us: https://homepage.cs.uiowa.edu/~jones/ternary/ https://homepage.cs.uiowa.edu/~jones/ternary/
- 7thaccount 2y agoDidn't the Russians develop a ternary computer system during the cold war?
- masswerk 2y agoSetun (1958) and Setun-70 (1970) https://en.wikipedia.org/wiki/Setun https://en.wikipedia.org/wiki/Setun
- kevmo314 2y agoHow did you manufacture your integrated circuits? I am very curious to learn about that process since it seems like it must be quite custom, or is there a neat way to reuse existing circuits?
- claudio_mos 2y agoWe do not currently have any integrated circuits, all the circuits (and PCBs) are entirely designed by me. What I said is that we are using a manufacturing process to do the VLSI layout to integrate everything into a single component, but currently it is not.
- cyberax 2y agoHey! You can run native Malbolge programs: https://en.wikipedia.org/wiki/Malbolge https://en.wikipedia.org/wiki/Malbolge !
- 1ncorrect 2y agoThe use case for Ternary logic I’m familiar with for is TCAMs in networking gear. https://en.wikipedia.org/wiki/Content-addressable_memory#Ternary_CAMs https://en.wikipedia.org/wiki/Content-addressable_memory#Ter...
- zamalek 2y agoI'm curious what the assembly looks like. Is it just normal binary Von Neumann running on your ternary processor, or is it something very different? Either way, great work. This is very fascinating.
- claudio_mos 2y agoThanks! Of course it can't be binary, but it reads purely ternary electrical signals. You can see an example of the assembly in one of the figures on the web page (even if it's an old listing). Expect all the normal operations a binary computer/processor does (load, store, jumps, subroutines, etc.) with the addition of ternary logic functions. It's clear that the whole thing is encoded in balanced ternary :)
- hoseja 2y agoBeautiful! Is the concept of balanced ternary semiconductor gates elaborated somewhere?
- claudio_mos 2y agoI have updated the site with a references section. Here you will find some links to recent studies on native ternary semiconductors.
- rep_lodsb 2y agoI would've expected some information on the architecture, maybe even a simulator. That should surely already have existed before any working hardware? Let's try to make sense of that code shown: ... jsr println anyi r3 r0 #1324 jsr println anyi r3 r0 #1412 jsr println hlt r0 appears to be the zero register, "anyi" combines that with an immediate to load a pointer to the string to print into r3. The immediate field is 12 trits, so we have a maximum address range of 531441 (trytes?) The encoding for the "jsr println" is always the same, so it's using absolute addresses, range is 3^20 or slightly less than 3.5G. Or would be if we were allowing negative addresses, since it appears to be balanced ternary (+--+00 = 144 decimal) Next bit of code is println, the address matches the one from jsr. println: ld r2 0(r3) ;get char jeq r2 r0 exit_println ;exit if nul out 50(r0) r2 ;output to console0? out 60(r0) r2 ;output to console1? addi r3 r3 #4 ;next char - why add 4? jmp println ;loop exit_println: anyi r4 r0 #10 ;ASCII LF out 60(r0) r4 ;output to console1? anyi r4 r0 #13 ;ASCII CR out 60(r0) r4 ;output to console1? jr r26 ;return (r26 = link register set by jsr) I'm not sure if this is supposed to be a word-addressed machine. Or would be better if it actually was. The addressing unit appears to be 6-trit "trytes", but loads only work when aligned to 4? Which seems a bit (no pun intended) inconvenient for a ternary computer! Is there no "load tryte" instruction? Jump instructions are encoded relative to the next instruction, with a 12-trit immediate. Seems fine, but a bit inconsistent with how jsr uses absolute addresses. Also again every instruction is 4 trytes, so we could drop the low bits and shift... ah, I'm forgetting that it's ternary, never mind. Separate I/O space, seems a bit un-RISCy. I personally happen to like x86, but even there it's considered a legacy feature nowadays. --- This may sound harsh, but to me the architecture looks both fairly conventional, and at the same time like a bit of a mess, which would be fine for a hobby project, but not for something with a website making grandiose claims and clearly intending to be a commercial product.
- claudio_mos 2y agoThat code in the figure is an old code, honestly it's an old screenshot that I don't even remember what it corresponds to, but your analysis is basically correct, even though I used absolute addresses before while now everything is relative to the current address. I'll try to answer a bit of everything: - yes, R0 is constantly set to 0. - ANYI is a ternary function (ANY) that uses an immediate (ANYI). It does nothing but load the immediate value into the register indicated as the first operand. - Yes, it is a balanced ternary, and clearly negative addresses are correctly interpreted >out 50(r0) r2 ;output on console0? out 60(r0) r2 ;output on console1? - Exactly. 50 and 60 are the addresses of the two serial ports on the motherboard. - R26 is the return register set by JSR -Addressing is at tryte level and an instruction is always 4 trytes long. You are right that it seems a bit strange, but it is a compromise that I had to accept and that I think was the best solution to implement. (I am happy to note that your doubt was also our strong doubt during the design phase, it means that we are considering the same problems...) -There are the dimensions of the data to operate on as a suffix of the instructions (like on motorola 68000) for which there is an LD.T (load tryte), LD.S (load short) and LD.W (load a whole word of 24 tries). There are also instructions that load/save by addressing the memory as if it were a stack for example PUSH.W (R20),R4 >Even again each instruction is 4 tries, so we could eliminate the low bits and >move... oh, I forgot that it is ternary, it does not matter. You think I didn't think about it? ;) - The IO space is separate, in the end it cost me almost nothing and I did it. The RISC features that I have kept are essentially 2: - Constant instruction length - Memory access only with Load/Store In fact among the RISC things that I could remove in a future version are precisely the single access to memory only with LD/ST, it is true that it is a main feature of RISC, but it is also true that it could be a problem for code density. But it is something that I will see on the 48-trit architecture >This may sound harsh, but to me the architecture looks both fairly conventional, and at the same time like a bit of a mess, which would be fine for a hobby project, but not for something with a website making grandiose claims and clearly intending to be a commercial product. -That it is "conventional" ok, (even if none of the conventional architectures are ternary, but whatever...) that it is messy, what do you mean? The website says what the project actually is. I'm glad they are grandiose things, but that's it. And yes, we want to become a commercial product soon. If you have suggestions or other specific questions, I'm here to answer you ;)
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- JKCalhoun 2y agoSuper cool. With the recent paper that apparently shows that ternary data used for AI can be faster and more energy efficient, I am intrigued that someone is experimenting with ternary in hardware. I am a layman — can a conventional computer architecture be taken and ternary data and instructions grafted on to it? Or does the whole architecture need to be rebuilt from the ground up? I guess I don't see, for example, any advantage to ternary addressing, only ternary data and operations.
- claudio_mos 2y agoThanks! Ternary data is definitely more efficient than binary, regardless of your use, not just for AI. I honestly don't know if it's faster, can you give me information on where you read that? I imagine it's possible even if quite difficult to merge the two architectures, but maybe it's really easier to start everything from scratch as far as hardware is concerned. What do you mean by ternary addressing? The address bus is also in ternary so even in this case fewer wires and more addresses available!
- mixmastamyk 2y agoWondering how negative voltage is routed around in hardware. Does it complicate things more or less than the increased data/addressing efficiency?
- whitten 2y agoI think it is a positive voltage which is interpreted as a negative number.
- JKCalhoun 2y agoProbably this one: https://arxiv.org/abs/2407.12327 https://arxiv.org/abs/2407.12327 But I suppose searching on "ternary LLM" would find others.
- Unbandit 2y agoSo, forgive me if I am wrong, but from my primitive YouTube "research", people said that the beauty of binary is that its relatively easy to see weather or not there is voltage, even with fluctuations of power. How does your processor compensate for that, meaning how does it measure out 3 different values. I could be wrong, and am willing to learn. But I enjoy your idea, and I am willing to help you especially when it comes to software.
- claudio_mos 2y agoJust as simple: it's easy to have positive voltage, negative voltage or no voltage ;) Thanks for the help, maybe we need someone to write the basic software right now!
- Unbandit 2y agoOh I see how it would work thank you. And ofc I am willing to work, just need to know the ISA and how you want it, maybe even a primitive emulator.
- jecel 2y agoDataflow processors have not been forgotten - there is one inside every high end CPU core. The code in main memory in the form of conventional x86 or ARM machine language gets translated first into "micro ops" in the decoder and then into dataflow machine language in the register rename + reservation stations + completion buffers (collectively implementing "out of order" execution). But, as the old saying goes, "out of sight is out of mind".
- claudio_mos 2y agoOh, I don't think at all that this method of operation (Tomasulo?) is remotely close to a real dataflow in terms of efficiency and complexity. But as I wrote, dataflow is another story ;)
- whitten 2y agoDo you use the idea of the previous post to store 5 ternary digits in one eight bit byte ? Discussed a few days ago here: https://news.ycombinator.com/item?id=42329307 https://news.ycombinator.com/item?id=42329307
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