callan

4 ms·

1.
by callan 14y ago
HLE is a pretty nifty implementation (note: I work for Intel) and an interesting use of CISC. IA instructions can optionally contain a prefix, such as LOCK, address and operand override (use 16, 32, or 64 bits), and repeat (REP). For exampl
2.
by callan 14y ago
I work for Intel. This is not correct. A lot depends on your cache type. The two basic ones are uncacheable and write-back. What you wrote is true for UC. For WB, reads can happen in any order (especially due to cache pre-fetchers). Writes
3.
by callan 14y ago
For those seeking more detail, Linux has a great reference on using memory barriers: http://www.kernel.org/doc/Documentation/memory-barriers.txt
4.
by callan 14y ago
I see this more as a "team builder"; a reminder why we are involved in our software communities. It's great to take a moment every once in a while (especially something historic like this) and give ourselves or others some recognition. Savv
5.
by callan 14y ago
Disclaimer: I'm a software guy @ Intel. I feel that a lot of sw folks have a lack of imagination when it comes to hw. A lot of very smart people here work on making an efficient, fast front-end. There's lots of research in this area. To my
6.
by callan 14y ago
NASA in fact did knit memories for the Apollo guidance computer. http://en.wikipedia.org/wiki/Core_rope_memory "Software written by MIT programmers was woven into core rope memory by female workers in factories. Some programmers nicknamed
7.
by callan 14y ago
The graphics in IVB are not just on the die, but are part of the internal memory ring and thus the shared L3 cache. So CPU cores are able to directly send and receive shared memory from the GPU, and the GPU is able to use the same last-leve
8.
by callan 14y ago
Also, there is a bit set after executing RDRAND that tells you if you got a 'good' random number.