I work for Intel. This is not correct. A lot depends on your cache type. The two basic ones are uncacheable and write-back. What you wrote is true for UC. For

I work for Intel. This is not correct. A lot depends on your cache type. The two basic ones are uncacheable and write-back. What you wrote is true for UC. For WB, reads can happen in any order (especially due to cache pre-fetchers). Writes always happen in program order, unless you are in other cache types such as write-combining. WC is mainly used for graphics memory-mapped pixmaps, where the order doesn't matter. But don't let this scare you too much. From the viewpoint of a single CPU, everything is in order. It's only when you look at it from the memory bus point-of-view that things get confusing. Unless we are dealing with a memory-mapped IO device that has read side-effects, in which case you need to carefully choose a cache type.