8 ms·
I did research in the field from 2008 to 2013. The claims are always the same: faster than flash, denser than dram, lower power than both. Here's how to spot B
by mmf 11y ago
I did research in the field from 2008 to 2013. The claims are always the same: faster than flash, denser than dram, lower power than both.
Here's how to spot BS: first, the density claims are immaterial until they prove yield at a technology node same as dram's today. There are multiple billions investment between 180nm and high yield (and low mask count) 2xnm, no matter how cool is the new memory technology.
Second, speed claims must be explicitly about latency: flash bandwidth is as large as you want it, latency is ~100us (read). Even so, the moment anybody claims that latency is faster than Dram, you know they're feeding the hype and lying to you: dram latency does not depend on the memory technology, rather it depends on the array size. So an 8Gb chip of any memory technology that is fast enough, is likely to be just as fast as dram.
Third: power consumption. Dram's active power is as low as it gets, the memory cell in particular stores information with really little energy. The array interconnect and circuitry consume most energy and a different memory technology won't change that.
- Symmetry 11y agoI think IBM found that the last level cache in their Power7 CPUs were faster with eDRAM than with SRAM because the reduction in transmission latency enabled by the smaller size made up for the higher cell latency so that's probably the crossover point where cell density wins over reasonable cell latencies. Of course memories with very large latency operations like a Flash erase can still dominate at much large sizes. And for off-die memory the transport is going to mask most differences anyways. The various sort of stacked memory coming into commercial use have the potential to reduce interconnect power and potentially make active RAM power at least slightly relevant. But I think the interesting thing about reducing RAM power consumption is decreasing passive power. Not that I expect anything to come of it for at least another half decade.
- russdill 11y agoActually you should be taking the claims very seriously. This has been an area Micron has been researching for decades. They've had a patent on the memory cell for about 11 years now (US6777705). Phase change memory has for a very long time been one of those just over the horizon technologies, but Micron has perfected it well enough to compete with NAND and partnered with Intel to bring it to market. This isn't something that appeared out of nowhere. Take a look at this presentation: https://www.micron.com/~/media/documents/products/presentation/gatwood_current_emerging_memory_landscape_fms2011_final.pdf https://www.micron.com/~/media/documents/products/presentati... Page 20 starts the section on "3-D Cross-Point Memory". They even have a 64Mb demonstrator on page 23, fabbed sometime before the 2011 Flash Memory Summit. Additional info on 64Mb demonstrator: http://investors.micron.com/releasedetail.cfm?releaseid=467247 http://investors.micron.com/releasedetail.cfm?releaseid=4672... Additionally, in early 2014, they stopped selling PCM modules, stating that "Micron's previous two generations of PCM process technologies are not available for new designs or technology evaluation, as the company is focused on developing a follow-on process to achieve lower cost per bit, lower power and higher performance." Job description details mentioning PCM, chalcogenides, and "cross point technology": https://www.linkedin.com/jobs2/view/12292797?trk=job_view_similar_jobs https://www.linkedin.com/jobs2/view/12292797?trk=job_view_si... And as far as process, as early as 2013 (2013 fall analyst conference handouts), Micron had PCM on a 45nm process and was listing 2xnm as next node. If they've gotten together with Intel and announced this, they have already reached 2xnm and/or beyond or are certain in their capability to do so. Because of the way flash memory is organized into pages and blocks, latency is very workload specific. Can you point out where anyone claimed it was better than DRAM latency?, the BBC article says "DRAM chips are still faster than 3D Xpoint, but the difference is much smaller than when compared with flash". And power consumption. This is PCM. Power consumption by the array when not being read/written is zero.
- russdill 11y agoForward looking article from June with tons of analysis http://seekingalpha.com/article/3253655-intel-and-micron-the-purple-swan http://seekingalpha.com/article/3253655-intel-and-micron-the...
- throw1111 11y agoNo, apparently it's not PCM. >While they did not specifically state it, it looks to be phase change memory (edit at the Q&A Intel stated this is not Phase Change). Source: http://www.pcper.com/news/Storage/Breaking-Intel-and-Micron-announce-3D-XPoint-Technology-1000x-Faster-NAND http://www.pcper.com/news/Storage/Breaking-Intel-and-Micron-...
- russdill 11y agoThe response in question has a lot of ah, uh's, and stutters: "Relative to phase change, which has been in the market place before and which micron itself has some experience with in the past again this is a very different architecture in terms of the place it fills in the memory hierarchy because it has these dramatic improvements in speed and volatility and performance" They didn't say that it wasn't PCM, and they didn't say that the technology was different. They said that the architecture was different than the PCM that Micron produced before. Which would be the cross-point organization and the all important selector element. They mention that the cell works my a "property change of the material", or a "bulk material property change". Go look up Micron's recent patents and applications. This is PCM. I do find it very interesting that they are bending over backwards not to call out the memory technology and specifically answering a question directly regarding if it is actually PCM.
- ncr100 11y agoThe video presentation mentioned "resistive". I'm not a memory nerd. Does that fact from their disclosure help at all narrow what this type of memory can be best categorized as? https://intel-micron-webcast.intel.com/webcast https://intel-micron-webcast.intel.com/webcast
- zxcv123 11y agoPower consumption of DRAM is high, what are you talking about? DRAM requires constant refresh -- the whole reason DRAM can be high-density if because it is a 1-T cell with a trench capacitor -- but the capacitor needs to be refreshed on a synchronized basis (hence SDRAM) -- that was the big innovation. And yes, array size affects latency but so does the underlying process technology (much more so across technologies).
- mmf 11y agoAs I did not have the numbers fresh in memory (apparently I needed a refresh ;) ) I googled for dram data sheet and got the first ddr3 PDF (Hynix). Quick, and very dirty math suggests that -refresh power is on the order of milliwats per Gigabyte -memory access is on the order of 0.1W per GB per second For refresh power, let's face it: it's puny. Regarding the active power, I have yet to see anything (off chip and this size) that is better than that. P.S. I did say active in my original post :)
- codebook 11y agoyou overlooked refresh time, which is around 7~8 ms. So, in order to keep the DRAM data alive, DRAM should consume a few tenths of Watt per Gigabyte per second, it is considerable amount of power.
- witty_username 11y agowatt per second makes little sense in this context watt != energy
- jjoonathan 11y ago> dram latency does not depend on the memory technology, rather it depends on the array size Wait, what? You mean they are making us wait 10ns for row open and 10ns for row close just for shits and giggles? Or did you mean to say "bandwidth"? I'm confused (genuinely, not sarcastically).
- mmf 11y agoNot shits and giggles, it's access to the array: subarray and word line decoding plus sense amp time. Find me a technology that does not need all these and I'll bow to you (and invest in your startup :D).
- jjoonathan 11y agoSRAM? I'm only half kidding. As a complete industry outsider it doesn't seem ridiculous to think that SRAM could do to DRAM what SSDs did to HDDs. Alas, I have no idea what the economics + trends are and I never did more than dabble in semiconductor engineering/physics so I will only ever find out after the fact.
- xxs 11y ago>>As a complete industry outsider it doesn't seem ridiculous to think that SRAM could do to DRAM what SSDs did to HDD SRAM needs 6 transistors per bit, DRAM 1transisitor+1capacitior. SRAM just doesn't scale and it's very expensive.
- jjoonathan 11y agoThanks for trying to be helpful, but this is both the most common and least believable explanation among those that I keep hearing. A constant factor between 3 and 6 kills SRAM's viability? DRAM is already over-provisioned by a factor of 2-4 even at the middle of the consumer spectrum just to support the "use case" of someone who can't be bothered to close their tabs. Going back to the hand-wavey analogy, SSDs stormed the scene with a ~50x constant factor disadvantage: http://www.kitguru.net/components/ssd-drives/anton-shilov/sandisk-to-release-8tb-ssd-in-2015-16tb-ssd-a-year-after/ http://www.kitguru.net/components/ssd-drives/anton-shilov/sa... If the only thing standing between SRAM and DRAM were a constant factor of <6, DRAM would already be history. The most convincing explanation I've heard is that caches are so damn good at hiding latency that getting rid of row open/close just doesn't matter. A few minutes of googling suggests that they often run at a 95% hit rate on typical workloads and a 99% hit rate on compute workloads. You would still need a cache even with main memory as SRAM to hide transit-time, permission checking, and address translation latency, so SRAM main memory wouldn't actually free up much die space, it would just make your handful of misses a bit faster (well, it would free up the scheduler / aggregator, but not the cache itself). The reason why I called this one "most convincing" rather than "convincing" is that even with a 99% hit rate a single miss has such atrocious latency that it would seem to matter.
- MaysonL 11y agoHow often does the BS include "going into production" and "sampling later this year"?
- mmf 11y agoHere: BS: "going into production this year" Possibly not BS: "going into production this year at 2x nam technology node with a y Gb part" Many nvm memory technologies, including mram and PCM have been "in production" for quite many years, with << 1Gb parts on old technology nodes, that is.