6 ms·

Is this like the Transmeta processors doing code translation in hardware?

LoganDark 21d ago
Transmeta did code translation with a software JIT. The hardware side had specific support for x86 semantics, similar to how Apple's M-series has supporting hardware for Rosetta's AOT translation, but neither executes x86 machine code directly.
stonogo 21d ago
They were pretty clear at Hot Chips that it's native
- pulse7 21d ago
  "code translation in hardware" microcode is called "native"
  - wahern 21d ago
    Yep. All modern Intel and AMD architectures, save maybe some Atom variants, effectively JIT compile the incoming instructions. It's part of the reason the faster-than-static Java/JVM promises never came to fruition. The goal posts moved after the mainstream chips coopted the approach, in a sense, and they continue to move as pipelines get deeper and broader and transistor count goes up. Transmeta was a classic failure--right idea, wrong place & time.
    - to11mtm 21d ago
      Eh? Intel and AMD were more or less 'Jitting' since the PPro and K5, and that's ignoring NexGen's Nx586 (which was shipping in hardware about a year before the PPro). All of them are way before Transmeta shipped a CPU. Where Transmeta tried to innovate was by using VLIW rather than a RISC-like core, along with their other special tech (Which they later licensed to lots of companies, including Intel,) to provide reasonable mobile performance with a low power draw. Oh, there's also the bit where Transmeta CMS is much more software based (likely, partially to push enough to software and avoid an x86 CPU license lawsuit) but even modern Intel chips AFAIK are still doing more translation on the CPU layer.
  - rbanffy 21d ago
    IBM’s microcode is really something. Not too long ago I heard about writing “millicode” as something that’s not at the microcode level, but not quite up at the ISA level.
    - bonzini 21d ago
      Millicode used custom extensions to the ISA but is otherwise regular s390 code. For example there is a separate register file and the "original" registers are available with either (I don't remember exactly) special instructions or special memory addresses. Intel by the way did the same for SGX, they called it xucode.
- to11mtm 21d ago
  .... I -so- miss RealWorldTech write-ups, I'd love to see what David Kanter would have to say about this thing...
  - ccgreg 21d ago
    David recently announced he was leaving MLCommons, so maybe we'll get him back as an industry analyst.
bryanlarsen 21d ago
No, this is more like any modern processor, which translates instruction codes into micro-ops. To over-simplify IBM just has two of these units per thread rather than one.
- christkv 21d ago
  I wonder how they handle potential differences in memory barriers, instruction order scheduling and other stuff and do they run the core in one mode continuously or do the mix instruction streams from different instruction sets? Anybody got a link to an article?
  - deleted 21d ago
    [deleted]
  - bryanlarsen 21d ago
    I had much the same question, which is one of the reasons I used the term "over-simplify". my guess is that many of the units have a toggle "arm mode / z mode", which would mean that mixing streams would be unlikely. I wonder if they chose ARM over x86 or other options partly because important aspects like the memory model of ARM and z were more similar than the memory models of x86 and z.
  - rbanffy 21d ago
    Possible different micro ops for different semantics. They also don’t mix instructions sets within the same process - the diagram I saw had ARM Linux as a guest under z/VM or KVM. For generations now no OS (not VM, not z/OS) hasn’t seen the bare metal machine, only ran under the PR/SM hypervisor, which is what does the logical partitions now. In order to properly run OSs for the 360 and 370 generations, s390x also has instructions for setting up CPU flags to more precisely emulate older machines. From an s390x binary you can, IIRC, do a jump to an address telling it that, from the jump forward the ISA is the one of a 360 until it encounters a return, which restores 390 mode.
    - pezezin 21d ago

Transmeta did code translation with a software JIT. The hardware side had specific support for x86 semantics, similar to how Apple's M-series has supporting hardware for Rosetta's AOT translation, but neither executes x86 machine code directly.

stonogo 21d ago

They were pretty clear at Hot Chips that it's native

pulse7 21d ago
"code translation in hardware" microcode is called "native"
- wahern 21d ago
  Yep. All modern Intel and AMD architectures, save maybe some Atom variants, effectively JIT compile the incoming instructions. It's part of the reason the faster-than-static Java/JVM promises never came to fruition. The goal posts moved after the mainstream chips coopted the approach, in a sense, and they continue to move as pipelines get deeper and broader and transistor count goes up. Transmeta was a classic failure--right idea, wrong place & time.
  - to11mtm 21d ago
    Eh? Intel and AMD were more or less 'Jitting' since the PPro and K5, and that's ignoring NexGen's Nx586 (which was shipping in hardware about a year before the PPro). All of them are way before Transmeta shipped a CPU. Where Transmeta tried to innovate was by using VLIW rather than a RISC-like core, along with their other special tech (Which they later licensed to lots of companies, including Intel,) to provide reasonable mobile performance with a low power draw. Oh, there's also the bit where Transmeta CMS is much more software based (likely, partially to push enough to software and avoid an x86 CPU license lawsuit) but even modern Intel chips AFAIK are still doing more translation on the CPU layer.
- rbanffy 21d ago
  IBM’s microcode is really something. Not too long ago I heard about writing “millicode” as something that’s not at the microcode level, but not quite up at the ISA level.
  - bonzini 21d ago
    Millicode used custom extensions to the ISA but is otherwise regular s390 code. For example there is a separate register file and the "original" registers are available with either (I don't remember exactly) special instructions or special memory addresses. Intel by the way did the same for SGX, they called it xucode.
to11mtm 21d ago
.... I -so- miss RealWorldTech write-ups, I'd love to see what David Kanter would have to say about this thing...
- ccgreg 21d ago
  David recently announced he was leaving MLCommons, so maybe we'll get him back as an industry analyst.

bryanlarsen 21d ago

No, this is more like any modern processor, which translates instruction codes into micro-ops. To over-simplify IBM just has two of these units per thread rather than one.

christkv 21d ago
I wonder how they handle potential differences in memory barriers, instruction order scheduling and other stuff and do they run the core in one mode continuously or do the mix instruction streams from different instruction sets? Anybody got a link to an article?
- deleted 21d ago
  [deleted]
- bryanlarsen 21d ago
  I had much the same question, which is one of the reasons I used the term "over-simplify". my guess is that many of the units have a toggle "arm mode / z mode", which would mean that mixing streams would be unlikely. I wonder if they chose ARM over x86 or other options partly because important aspects like the memory model of ARM and z were more similar than the memory models of x86 and z.
- rbanffy 21d ago
  Possible different micro ops for different semantics. They also don’t mix instructions sets within the same process - the diagram I saw had ARM Linux as a guest under z/VM or KVM. For generations now no OS (not VM, not z/OS) hasn’t seen the bare metal machine, only ran under the PR/SM hypervisor, which is what does the logical partitions now. In order to properly run OSs for the 360 and 370 generations, s390x also has instructions for setting up CPU flags to more precisely emulate older machines. From an s390x binary you can, IIRC, do a jump to an address telling it that, from the jump forward the ISA is the one of a 360 until it encounters a return, which restores 390 mode.
  - pezezin 21d ago