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RISC-V is now officially supported by CPython
- yjftsjthsd-h 19d ago> RISC-V is now officially supported by CPython as a tier 3 platform! That's significant, but tier 3 is still a caveat. Still allowed to break without blocking anything or being fixed as a priority.
- jmalicki 19d agoSure, but I had to look: Tier1: Windows x64/i686, Linux x64/ARM gcc, Darwin/ARM Tier2: Linux x64/ARM w/ clang, Windows ARM, WASM, Darwin/x64 Tier3 is a pretty low support level, but tiers 1 and 2 is a pretty short list of major commercial platforms. Also even for developers to fix, availability of e.g. RiscV machines in the cloud to reproduce and fix on is still somewhat limited.
- zxexz 19d agoWindows i686, tier 1, what? I’ll do some digging when I’m home but I feel the sudden need to understand this.
- digkls 19d agoRISC-V is one of those experimental architectures that hardly anyone is actually using, isn't it? Tier 3, or no support at all, seems an appropriate designation.
- boredatoms 19d agoNot much on user facing OS, but billions of small controllers
- yjftsjthsd-h 19d agoI don't think CPython targets those, though; that seems more like a micropython thing?
- deleted 19d ago[deleted]
- phire 19d agoNeeds to start somewhere. Looks like the most important step towards tier two is mostly about proving the CI infrastructure is reliable (which takes time at tier 3), and have at least two core developers committed to fixing any issues (within 24 hours)
- boredatoms 19d agoAtleast CI-class hardware finally exists, with the sifive bigsky https://www.sifive.com/development-platforms/sifive-bigsky-sf-2u870-datacenter https://www.sifive.com/development-platforms/sifive-bigsky-s...
- fenestella 19d ago[dead]
- ironhaven 19d agoWhat RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against. It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance with a python interpreter. I guess more testing needs to be done to see if raising the bar is useful. [1]https://www.sifive.com/cores/performance-p800 https://www.sifive.com/cores/performance-p800
- londons_explore 19d agoRISC-V fragmentation bites again...
- orangeboats 19d agoThe same problem exists for x86. Is $program built for x86-64 with SSE2? AVX2? AVX512? (I chose those three because they are programmer-visible. Programmers have to use intrinsics to exploit those ISA extensions effectively.) For RISC-V the questions to ask are similar: Is this built for RVA20? Or RVA23? (The big feature of RVA23 is the Vector extension, again something that is programmer-visible) Embedded RISC-V programmers will have to ask a lot more questions. But for most programmers the whole fragmentation thing is simply a giant meme repeated ad nauseam.
- mort96 19d agoIntel has done such a good job keeping AVX512 support away from reaching ubiquitous adoption, it's insane. There are so many useful instructions in AVX512 which are just missing from AVX/AVX2 that you can't assume exist, even on modern CPUs, because Intel can't get their shit together. The core problem was tying instructions to bit width. But I'm actually surprised that they didn't add AVX512 support through double pumped 256-bit operations like AMD did for a while.
- Karliss 19d agoPeople bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores. On x86 situation is even crazier https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html . Some of the more recent CPUs list ~60 optional features. Even if you look just at generic common profiles you have i386, i486, i586, i686, x86-64, x86-64-v2, x86-64-v3, x86-64-v4. Just a single family of vector instructions has 6 different versions for example: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2. I am not even going to try counting all the variations and optional instructions of AVX512. On one hand this is an important topic, especially in contexts like which X86-64 profile are the software in Linux distro official repositories targeting. At the same time no one is bothered by 20 cent ARM mcu not having instructions for atomic memory access, supervisor, SIMD or even floating point. So if anything RISC-V instruction set optional feature sets are probably better structured and less fragmented (for now) than the current situation with ARM and x86.
- yyyk 19d agoOdd they still have i686-pc-windows-msvc as Tier 1 *. Even Microsoft doesn't have any supported 32bit Windows versions anymore, and C extension modules likely follow Linux (where Python doesn't have any no supported i686 triplets in any tier). It would be more modern to demote its Tier and promote aarch64 Windows or wasm32 instead to Tier 1. * https://peps.python.org/pep-0011/#tier-1 https://peps.python.org/pep-0011/#tier-1
- woodruffw 19d agoPython's tiering has to do with testability and availability thereof, not modernness. In the case of 32-bit Windows, the reason it's still testable is because Windows still ships a 32-bit userspace, even if Windows itself only supports x86-64. (From personal experience, testing Windows aarch64 is a massive PITA, even on GitHub Actions, which all common sense would indicate should have the best aarch64 Windows CI runner story.)
- yyyk 17d agoThat explains Tier-2 vs Tier-3. Not Tier-1 (where i686-windows is) vs Tier-2. Demanding every commit pass CI is a project decision.
- scam-alt-human 19d ago[flagged]
- zopppo 19d agoHow is Python a dead language due to ML when it's the lingua franca of AI/ML between pytorch, pandas, numpy, langchain, litellm, vLLM, and a whole bunch of other libraries?
- __patchbit__ 19d agoUnison.
- gagan2020 19d agoCan we do something about CPython Global Interpreter Lock (GIL)?
- greatgib 19d agoFor quite some times I'm wondering how I could invest in RISC, or RISC related manufacturer but it looks like all companies are private.
- deleted 19d ago[deleted]
- boredatoms 18d agoCheck out Hiive and make a bid if you want Sifive stock also Andes is public
- greatgib 18d agoSadly I think that Hiive is restricted to US based investors.
- throwaway81523 19d agoCPython is written in C, did running it on Risc-V take more than a recompilation? Were there any surprises? Yes of course it needs testing and RISC-V in the CI stack, but I'd expect fairly smooth sailing.
- tyingq 19d agoThere is a Configure type subsystem, so you'll see stuff like this: https://github.com/python/cpython/pull/156277/changes#diff-49473dca262eeab3b4a43002adb08b4db31020d190caaad1594b47f1d5daa810 https://github.com/python/cpython/pull/156277/changes#diff-4...
- emmatyping 19d agoIn short, we haven't found many bugs, but it also wasn't just recompile on a new platform. We've seen test failures like https://github.com/python/cpython/issues/151040 https://github.com/python/cpython/issues/151040 And perf support needs to be tested and merged https://github.com/python/cpython/issues/121201 https://github.com/python/cpython/issues/121201 Overall though, fairly smooth sailing as you say. The reason RISC-V wasn't already supported is a mix of lacking hardware access for build bots and committers willing to pledge time to support it.
- shash 19d agoWe ran it 4 years ago (including numpy) and it wasn’t a massive uphill climb or anything. It’s gotten a little easier since then if anything.
- rzulasf 19d ago[flagged]
- tlk-22815 18d agoWe ran python-3.14 on RISC-V before switching to C++ only. It compiled without any errors and all tests passed. I don't understand the significance of this announcement in the submission.
- Qem 19d agoDid they already test how the proposed jit fares on RISC-V?
- jartan2002 18d ago[flagged]
- saint-evan 18d agoWe got RISC-V support before an official 3.14t docker image.
- vrighter 18d agowhen I designed my own simple risc-v processor with just rv32i, i just compiled lua. Hassle free