6 ms·

Taalas will be one of the great disaster investments of the early AI era. It'll be a near total write-down. The absolute worst market time to etch a model to a

Taalas will be one of the great disaster investments of the early AI era. It'll be a near total write-down. The absolute worst market time to etch a model to a chip is right now (very rapid iteration). There is no scenario where they can keep up. The Taalas approach will be viewed as comically foolish within just a few years. Cerebras will win in terms of approach. It's 1998: hey, I can drastically speed up your web service, let's etch it right to silicon.

moralestapia 29d ago
It's 2026: let's etch nginx into silicon and get 10,000,000 rps at a cost of 0.1 US/day. Yes, please!
- redox99 29d ago
  Most people probably don't care about nginx performance. It shouldn't be your bottleneck unless you serve massive amounts of static data.
  - dyzone 29d ago
    Ok, how about postgres?
  - mdp2021 29d ago
    In the case of needs to process natural language, instead, massive efficiency (esp. time) can be a game changer. It's like "you have two years to complete the project" vs "you have two hours to complete the project": if you can squeeze that "two years worth" into a negligible delay, it's a game changer.
alightsoul 29d ago
maybe AMD wants the IP to deploy it once ai model development slows down in a few years. Or, their large cloud customers do want to burn through silicon, basically paying rent to AMD for models etched on silicon.
pimeys 29d ago
I just want to but hardware so I can run a model at home that is fast. I don't see myself installing a server that burns almost two hundred kilowatts but maybe a card which runs a 27B Qwen...
- mdp2021 29d ago
  At 250w when it's working (I understand), and it works for tiny amounts of time per query...
  - mdp2021 28d ago
    Corrige: a Taalas HC1 PCIe card consumes actually between ~200W and ~250W (a 10 blades server consumes ~2500W).
NitpickLawyer 29d ago
> The absolute worst market time to etch a model to a chip is right now Slightly disagree. It really depends on the price-point at which they can do that etching. ~1k usd / ~30B model in a hdd-sized case that fits on your desk? I'd buy one right now, even knowing that I'm "stuck" with whatever model of the day is.
- riknos314 29d ago
  Time to market also matters a ton. If they can start shipping chips <1 month after the weights drop that's much more compelling than if it's a 6+ month development pipeline.
  - mdp2021 29d ago
    In the case of Taalas, the pipeline was said to be 2 months: > From the moment a previously unseen model is received, it can be realized in hardware in only two months ( https://taalas.com/the-path-to-ubiquitous-ai/ https://taalas.com/the-path-to-ubiquitous-ai/ )
Iolaum 29d ago
I would still pay ~500 for a chip that runs 10kt/s of a ~100b model on my machine even if the half life is 6months. I m sure my employer would too. Qwwen3.5 122b was released 6 months ago and is still best in class overall 100-140 B param model.
- jeffybefffy519 29d ago
  10000%
- x-complexity 29d ago
  > I would still pay ~500 for a chip that runs 10kt/s of a ~100b model on my machine even if the half life is 6months. .... :T Considering the 8B model uses 53 billion transistors, that's 6.625 transistors per parameter. https://taalas.com/products/ https://taalas.com/products/ Assuming they can get it down to 3 (somehow), that's still 300 transistors, or 5.565 RX 9070s. https://www.techpowerup.com/gpu-specs/radeon-rx-9070.c4250 https://www.techpowerup.com/gpu-specs/radeon-rx-9070.c4250 You're looking at 1) waiting for another 3-5 generations of transistor improvements before it can fit into a single conventional chip, or 2) another generation before getting a monster of a chip (1000+ mm^2), and prices for flawless etching scale quadraticly (likely $1000+ for manufacturing costs alone). Could happen, but it's a long shot for a market that could be satiated by specialized accelerators.
  - mdp2021 29d ago
    In Taalas HC2 a chip embeds 20b parameters, and the declared idea is linking the chips. A card with two of them chips and you can already have a dense Qwen at staggering speeds.
    - x-complexity 28d ago
      Chiplet-style layouts could cut the etching quality requirements per chip down, but it still can't avoid the base cost for manufacturing silicon.
      - 28d ago
conception 29d ago
Etched model into a chip? A… mobile chip eventually? Seems prescient.
WithinReason 29d ago
The 500x efficiency gain makes their approach a no brainer. Just make a new chip every 6 months, you still win.
- supersour 28d ago
  Yes, power efficiency may be the largest benefit of these chips actually - especially if the projections are true that the US and other countries simply aren't able to ramp up power generation to meet forecasted datacenter demand. There's a bit of a ticking time bomb there, something that a Taalas-like architecture can clearly resolve.
walrus01 29d ago
> It's 1998: hey, I can drastically speed up your web service, let's etch it right to silicon. I distinctly remember 32-bit/33 MHz PCI accelerator cards for SSL being a real thing (for use on OpenBSD or FreeBSD), in an era when something like a single core 700 MHz Pentium 3 1U system was a relatively powerful individual bare metal httpd box. http://www.aster.si/partnerji/compaq/atalla/axl200.html http://www.aster.si/partnerji/compaq/atalla/axl200.html The CPU load of doing a lot of SSL purely in software was a problem in terms of scaling things up, so this was one attempt at a (very short lived) solution. Note that this predated TLS1.0.

moralestapia 29d ago

It's 2026: let's etch nginx into silicon and get 10,000,000 rps at a cost of 0.1 US/day. Yes, please!

redox99 29d ago
Most people probably don't care about nginx performance. It shouldn't be your bottleneck unless you serve massive amounts of static data.
- dyzone 29d ago
  Ok, how about postgres?
- mdp2021 29d ago
  In the case of needs to process natural language, instead, massive efficiency (esp. time) can be a game changer. It's like "you have two years to complete the project" vs "you have two hours to complete the project": if you can squeeze that "two years worth" into a negligible delay, it's a game changer.

alightsoul 29d ago

maybe AMD wants the IP to deploy it once ai model development slows down in a few years. Or, their large cloud customers do want to burn through silicon, basically paying rent to AMD for models etched on silicon.

pimeys 29d ago

I just want to but hardware so I can run a model at home that is fast. I don't see myself installing a server that burns almost two hundred kilowatts but maybe a card which runs a 27B Qwen...

mdp2021 29d ago
At 250w when it's working (I understand), and it works for tiny amounts of time per query...
- mdp2021 28d ago
  Corrige: a Taalas HC1 PCIe card consumes actually between ~200W and ~250W (a 10 blades server consumes ~2500W).

NitpickLawyer 29d ago

> The absolute worst market time to etch a model to a chip is right now Slightly disagree. It really depends on the price-point at which they can do that etching. ~1k usd / ~30B model in a hdd-sized case that fits on your desk? I'd buy one right now, even knowing that I'm "stuck" with whatever model of the day is.

riknos314 29d ago
Time to market also matters a ton. If they can start shipping chips <1 month after the weights drop that's much more compelling than if it's a 6+ month development pipeline.
- mdp2021 29d ago
  In the case of Taalas, the pipeline was said to be 2 months: > From the moment a previously unseen model is received, it can be realized in hardware in only two months ( https://taalas.com/the-path-to-ubiquitous-ai/ https://taalas.com/the-path-to-ubiquitous-ai/ )

Iolaum 29d ago

I would still pay ~500 for a chip that runs 10kt/s of a ~100b model on my machine even if the half life is 6months. I m sure my employer would too. Qwwen3.5 122b was released 6 months ago and is still best in class overall 100-140 B param model.

jeffybefffy519 29d ago
10000%
x-complexity 29d ago
> I would still pay ~500 for a chip that runs 10kt/s of a ~100b model on my machine even if the half life is 6months. .... :T Considering the 8B model uses 53 billion transistors, that's 6.625 transistors per parameter. https://taalas.com/products/ https://taalas.com/products/ Assuming they can get it down to 3 (somehow), that's still 300 transistors, or 5.565 RX 9070s. https://www.techpowerup.com/gpu-specs/radeon-rx-9070.c4250 https://www.techpowerup.com/gpu-specs/radeon-rx-9070.c4250 You're looking at 1) waiting for another 3-5 generations of transistor improvements before it can fit into a single conventional chip, or 2) another generation before getting a monster of a chip (1000+ mm^2), and prices for flawless etching scale quadraticly (likely $1000+ for manufacturing costs alone). Could happen, but it's a long shot for a market that could be satiated by specialized accelerators.
- mdp2021 29d ago
  In Taalas HC2 a chip embeds 20b parameters, and the declared idea is linking the chips. A card with two of them chips and you can already have a dense Qwen at staggering speeds.
  - x-complexity 28d ago
    Chiplet-style layouts could cut the etching quality requirements per chip down, but it still can't avoid the base cost for manufacturing silicon.
    - 28d ago

conception 29d ago

Etched model into a chip? A… mobile chip eventually? Seems prescient.

WithinReason 29d ago

The 500x efficiency gain makes their approach a no brainer. Just make a new chip every 6 months, you still win.

supersour 28d ago
Yes, power efficiency may be the largest benefit of these chips actually - especially if the projections are true that the US and other countries simply aren't able to ramp up power generation to meet forecasted datacenter demand. There's a bit of a ticking time bomb there, something that a Taalas-like architecture can clearly resolve.

walrus01 29d ago

> It's 1998: hey, I can drastically speed up your web service, let's etch it right to silicon. I distinctly remember 32-bit/33 MHz PCI accelerator cards for SSL being a real thing (for use on OpenBSD or FreeBSD), in an era when something like a single core 700 MHz Pentium 3 1U system was a relatively powerful individual bare metal httpd box. http://www.aster.si/partnerji/compaq/atalla/axl200.html http://www.aster.si/partnerji/compaq/atalla/axl200.html The CPU load of doing a lot of SSL purely in software was a problem in terms of scaling things up, so this was one attempt at a (very short lived) solution. Note that this predated TLS1.0.