8 ms·
Samsung Foundry Forum announcements
- spark3k 5y agoAt what point does quantum tunnelling become a problem?
- hajile 5y agoFrom a few years ago until we perfect the QFET and can put it to use.
- codefined 5y agoQuantum tunnelling has already become a problem in most computer components. NAND flash was the first in maybe 2015 to start reporting seeing issues? Effects are moderately visible and have to be counteracted at 5nm. I heard some rumours about 7nm, but cannot confirm any countermeasures were taken to avoid quantum effects. It should be noted that "3nm" is now purely for commercial reasons and has no relationship to the size of transistors on board.
- wetpaws 5y agoIt's always been a problem to some degree. Keep in mind that 3nm is a misnomer and has no real physical meaning behind it.
- deleted 5y ago[deleted]
- deleted 5y ago[deleted]
- weatherlight 5y agoFirst though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now. The really concerning physical dimension for quantum tunneling to occur/not occur is "gate length," and that's been basically sitting around ~16nm (actual, real, literal 16nm), plus or minus a few nanometers (depending on the manufacturer and process in question), since about "45nm" (mid-late 2000s). So that one critical dimension isn't getting smaller. And there isn't much they can do about it right now. They are still shrinking other dimensions though, and things don't work like they used to. Powered off transistors aren't really off, and leak power. The workaround for this is that they just use bigger transistors in certain places for what's called "power gating". You get the benefits of having tons of small transistors, with a slight area penalty. In addition to power gating, they have made substantial improvements to the design of the transistors themselves. Gates now wrap around the channel on 3 sides, creating a device known as a Finfet. Silicon dioxide is no longer used as an insulator to the same extent -- hafnium dioxide preforms much better as an insulator. Gates are now metal instead of polysilicon. And there's an assortment of other changes that have occurred or are on the way. So performance has actually managed to improve somewhat, and things have still gotten smaller. The end is near... but not quite yet. Gate length is not going to budge much unless some miracle occurs, though.
- baybal2 5y agoThe theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
- Misdicorl 5y agoCan't they use a smaller wavelength source? Nothing special about 13nm afaik
- Filligree 5y agoThe design of EUV lasers is already completely absurd. It's an awesome piece of engineering, but it's no easier to push the laser wavelength downwards than anything else.
- Misdicorl 5y agoDoes the lithography require the tight wavelength or other nice properties of lasers? I had thought they used filtered synchrotron output since a while ago. Basically everything about the process is absurd, not sure why pushing on the light source is less feasible then any of the other knobs
- lazide 5y agoDiffraction limit becomes a real problem at these feature sizes even with short wavelength light, and the physical properties of short wavelength light start to damage equipment and cause serious other issues even at the current levels. At some point it’s switching from ‘lots of wiffle balls in a stream’ to ‘high power machine gun fire’, and the physical properties of everything involved become very limiting.
- sbierwagen 5y ago13nm is hard enough. ASML seems to have settled on laser-driven tin plasma light source, which is miserably inefficient: https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph >The required utility resources are significantly larger for EUV compared to 193 nm immersion, even with two exposures using the latter. Hynix reported at the 2009 EUV Symposium that the wall plug efficiency was ~0.02% for EUV, i.e., to get 200-watts at intermediate focus for 100 wafers-per-hour, one would require 1-megawatt of input power The optical train is also tough. 13nm is getting close to soft x-rays, and photons that hot don't like reflecting, and the optics are rapidly degraded by exposure light: >EUV collector reflectivity degrades ~0.1-0.3% per billion 50kHz pulses (~10% in ~2 weeks), leading to loss of uptime and throughput [...] Due to the use of EUV mirrors which also absorb EUV light, only a small fraction of the source light is finally available at the wafer. There are 4 mirrors used for the illumination optics, and 6 mirrors for the projection optics. The EUV mask or reticle is itself an additional mirror. With 11 reflections, only ~ 2% of the EUV source light is available at the wafer.
- k0stas 5y agoIt already has been a problem in terms of gate leakage, although largely mitigated by material improvements. Gate leakage is the phenomenon of quantum tunneling through the gate dielectric barrier and started appearing as gate dielectrics became thinner and thinner. Gate leakage was mitigated by moving to higher k dielectrics (from silicon dioxide, SiO2, to more exotic materials that include other elements such as Hafnium). Higher k dielectrics allow for the same capacitance per unit area and channel control with a thicker physical gate compared to plain SiO2, reducing gate leakage. This technology change came along with metal gates (which used to be polysilicon) and were a combined advance that Intel incorporated a few years before before TSMC, IIRC circa 2008. This is a circuit designer's perspective. Someone who actually understands device physics and material properties can chime in to correct me.
- catmanjan 5y agoThere are a few comments saying that 3nm is a marketing term and that the transistors are actually larger - how is this allowed? Isn't it misleading and deceptive?
- colechristensen 5y agoThere’s not really a standard, some feature is probably 3nm, which feature chosen has varied over time and between companies.
- adrian_b 5y agoThere are no features with lengths of 3 nm, 7 nm etc. Some vertical distances, e.g. thicknesses, are indeed of only a few nm, but the process size name always referred strictly to horizontal distances (i.e. parallel with the wafer surface), which are determined by lithography. Those are at least 10 times larger, in the range 25 nm to 60 nm for modern processes. There are a few horizontal distances that are not determined by lithography, i.e. they do not correspond with something drawn on the mask, but the distances are determined by speeds of corrosion or diffusion, like also for the vertical dimensions, but those also do not count for naming processes, because you could have such a distance of only e.g. 5 nm even in an 180 nm process. Those distances that are not determined by lithography do not influence the potential density of a circuit but only certain electrical performances.
- baybal2 5y agoActually it is all about marketing now, the customers though to whom they market are MNCs with immense cash piles to splurge on microchips. Nobody else can. See — you rarely ever see so much marketing money spent on an industrial service, and like here seeing Hollywood level gfx on an obscure industry event keynote would've been more laughable than noteworthy 10 years ago. Without these cash piles, there is no way to finance new fabs, and SEL is fighting for its survival here. Once you are out of the race in semi industry, you can never catch up.
- marcosdumay 5y agoWell, I hope nobody chooses a fab based on the headline number on their marketing material. Adapting your design to them is a long process that requires all kinds of details, and how well they will produce your circuit depends on those details as much as on the feature size.
- 1-6 5y agoSamsung has a dishonorable marketing department. 3nm is not actually 3nm. I'm fed up... OLED is superior so they had to take the path of calling theirs QLED which is actually just an LCD screen with phosphors on top of a blue backlight (and it's nothing new).
- imtringued 5y ago3nm means the process is equivalent in density and performance to a 3nm planar transistor that Samsung designed. I don't see how that is dishonorable marketing because every company designed their own reference planar transistors.
- wyattpeak 5y ago> 3nm is not actually 3nm It's a stretch to blame that on Samsung, processor generations described in nanometres haven't been based on actual component size for years now, by any manufacturer.
- KronisLV 5y agoI feel that if numbers were all wrong in, say, the automotive or aerospace industries, there'd be more of an upheaval about it. Then again, the nanometer sizes aren't always completely indicative of performance and aren't necessary to be used in any capacity when actually using a computing device, so maybe it's not as bad. Dishonest marketing, though? Most certainly.
- rurounijones 5y agoGamersNexus on Youtube have a great video detailing all the issues with processor naming with regards to sizing. https://www.youtube.com/watch?v=wxKGFxmwcDo https://www.youtube.com/watch?v=wxKGFxmwcDo
- MikusR 5y agoAnd cpus are just sand
- marcodiego 5y agoWhat is the best metric nowadays? Dhrystones/MIPS/FLOPS per MHz/Watt per square inch? As a complete outsider, millions of transistors per square inch sounds like a very intuitive metric of how small things are.
- MangoCoffee 5y ago> process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure I believe GAA is the next gen tech for the node process. Samsung is the first foundry to do GAA w/3nm while TSMC is sticking w/FinFET for their 3nm. It'll be interesting to see how 3nm FinFET compare to 3nm GAA. https://www.anandtech.com/show/16041/where-are-my-gaafets-tsmc-to-stay-with-finfet-for-3nm https://www.anandtech.com/show/16041/where-are-my-gaafets-ts... edit: >After that, transistor structures begin to change. Samsung and TSMC are manufacturing chips at 7nm and 5nm based on today’s finFETs. Samsung will move to nanosheet FETs at 3nm. Intel is also developing GAA technology. TSMC plans to extend finFETs to 3nm, and then will migrate to nanosheet FETs at 2nm around 2024. https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/ https://semiengineering.com/the-increasingly-uneven-race-to-...
- hajile 5y agoIntel's switch to FinFET was equivalent to almost 2 node jumps. If they nail GAA, then it will probably be much better, but it will also be enormously more expensive to produce the chips. Intel has loads of cash and would pay that money in a second, but I suspect that most other companies would rather hold off a bit longer in exchange for much cheaper products.
- baybal2 5y ago> I believe GAA is the next gen tech for the node process. Samsung is the first foundry to do GAA w/3nm while TSMC is sticking w/FinFET for their 3nm. It'll be interesting to see how 3nm FinFET compare to 3nm GAA. Comparing Apples to Oranges, and doing doing a comparison on taste vs. size. The device may well be awesome, but first ICs using it not so. The biggest advancements in under 14nm were in metal, not so much with the device, process, or materials. Even if Samsung will produce a better device design, they will still have to catch up to TSMC in so many, many other areas. Only single digit number of people on this planet will ever know the exact measurements of FinFet vs. GAAFet But one thing for sure, Samsung saying that they pioneered a new device ahead of TSMC does indeed sound very, and impressive to a certain category big co. people regardless of actual performance.
- deleted 5y ago
- pabs3 5y agoHmm, I wonder how this compares to TSMC/Intel in terms of transistor density? Is transistor density the best measure of chip competitiveness these days?
- yboris 5y ago> Samsung To Mass Produce 2nm Chips in 2025 https://www.tomshardware.com/news/samsung-foundry-to-produce-2nm-chips-in-2025 https://www.tomshardware.com/news/samsung-foundry-to-produce...
- kulor 5y agoFor silicon n00bs like myself, listen to Acquired's recent episode for some context on how hard this area of innovation is https://www.acquired.fm/episodes/tsmc https://www.acquired.fm/episodes/tsmc. Off the back of this episode, I can't help but feel TSMC's monopoly needs disrupting with players like Samsung to contend with Taiwan & China's geopolitical tension.
- hokumguru 5y agoAt what point do we have to stop because we’ve hit physical limits? At 3nm we are talking transistors only a few dozen atoms wide, what’s the smallest theoretical transistor we can build?
- weatherlight 5y ago3nm is a marketing term.
- marcosdumay 5y agoWith the old-school plane transistors over the wafer's silicon design, you need about 10nm of doped material so it won't completely mix with everything else. With theoretical organic 1-electron designs you can build a transistor out of 4 carbon atoms. But nobody knows how to mass produce those ones. We are somewhere on the middle, modern designs did break the 10nm barrier, but are not nearly as small as those numbers you see around.
- mhh__ 5y agoThe actual feature sizes are still (remember these shapes are 3D) quite a few scalings away from being even close to atoms.
- nabaraz 5y agoI can never remember what xnm means as it varies between companies. In this case, Samsung's 3nm = Intel's 7nm I am still waiting for a standard based on transistor density numbers!
- nicoburns 5y agoIntel actually renamed their nodes in like with Samsung and TSMC, so Intel 7 (used to called 10nm) is roughly comparable to TSMCs 7nm and Samsungs 8nm
- atty 5y agoFor anyone who had not been aware (like me), apparently Intel has renamed their third gen 10 nm process to 7, and their 7 nm process (the one that they describe as being their first full use of EUV, that got pushed back to 2023) is now named 4. That puts Intel’s node naming roughly in line with TSMC and Samsung in terms of feature density.
- soylentnewsorg 5y agothere was a restaurant, a&w I think, which had a 1/3lb burger. a whole bunch of people thought it was a ripoff - smaller than a quarter pounder. As it's impossible to explain to the masses that they need to repeat 3rd grade, the restaurant gave up on the idea. then there was windows. have you actually heard an elite hipster tell you, a professional highly paid tech guy, that mac is superior because windows is behind on operating systems? not because unix is better. no, because windows was "8" and mac was "10." X is the roman numeral for "10" you see, and 10 is a later version than 8. So ms ended up skipping windows 9. There was a defined standard for process sizes. A bunch of unethical marketing scammers used half-truths to scam people. It worked, because people can't even figure out a hamburger. And now the people who followed the long-established standard have to switch to the scammer's standard, because they still need that hamburger guy's money. Here's the problem with customers... You need their money.
- AmericanChopper 5y agoIt doesn’t relate to any measurement of feature size. It’s just a frustratingly meaningless marketing term.
- freen 5y agoIf their chip fan has the same commitment to QA as their TV’s, I’ll pass.