xoranth

8 ms·

1.
by xoranth 2y ago
> Crappy Pixel Fold 2022 mid-range Android CPU Can you share what LLMs do you run on such small devices/what user case they address? (Not a rhetorical question, it's just that I see a lot of work on local inference for edge dev
2.
by xoranth 2y ago
Are there any good how-tos for how to set up a non-trivial container with s6 and s6-rc? Last time I looked at this the documentation was pretty sparse, and more of a reference and design document than a set of how-tos.
3.
by xoranth 2y ago
I believe they mean that since it bypasses the (Tokio) scheduler, so if you use it in async code you lose the main benefit of async code (namely, the scheduler is able to switch to some other task while waiting for IO to complete.). Basical
4.
by xoranth 2y ago
On Linux, you might be able to use userfaultfd to make it async...
5.
by xoranth 2y ago
Thank you for your reply! > GPUs are also just generally a lot more limiting than SIMD in many other ways. What do you mean? (besides things like CUDA being available only on Nvidia/fragmentation issues.)
6.
by xoranth 2y ago
Sure, but how well do they perform compared to vector loads? Do they get converted to vector load + shuffle uops, and therefore require a specific layout anyway? Last time I tried using gathers on AVX2, performance was comparable to doing s
7.
by xoranth 2y ago
General questions for gamedevs here. How useful is SIMD given that now we have compute shaders on the GPU? If so, what workloads still require SIMD/why would you choose one over the other?
8.
by xoranth 2y ago
On x86-64, compilers use SIMD instructions and registers to implement floating point math, they just use the single lane instructions. E.g. ( https://godbolt.org/z/94b3r8dMn ): float my_func(float lhs, float rhs) {
9.
by xoranth 2y ago
Sounds a bit like Google's proposal for a `switchto_switch` syscall [1] that would allow for cooperative multithreading bypassing the scheduler. (the descendants of that proposal is `sched_ext`, so maybe it is possible to implement doo
10.
by xoranth 2y ago
Thanks!
11.
by xoranth 2y ago
Is the extension you wrote public?
12.
by xoranth 2y ago
How would this interact with `io_uring`, especially the polling modes (IO_SETUP_SQPOLL, IO_SETUP_IOPOLL)?
13.
by xoranth 2y ago
I believe the reason they offer no details about how they tuned the kernels is that the tuning is done by a tool provided by AMD. See here: https://rocm.docs.amd.com/projects/rocBLAS/en/develop/how-to...
14.
by xoranth 2y ago
Is there any good article on NT internals (that isn't Russinovich' book), that highlight where/how it is better than Linux and other *BSDs? When asked people point to IOCP vs epoll, but I'm not sure how relevant it is no
15.
by xoranth 2y ago
> expression templates That's one of the cases where you can't "mechanically" translate C++ to Rust. To obtain the same result, a good choice would be a proc macro. Which is a pain to implement, but will also give you
16.
by xoranth 2y ago
Thanks!
17.
by xoranth 2y ago
> That allows things like individual threads to take locks, which is a pretty big leap. Does anyone know how those get translated into SIMD instructions. Like, how do you do a CAS loop for each lane where each lane can individually succe
18.
by xoranth 2y ago
Do you know any good tutorial for ISPC? Documentation is a bit sparse.
19.
by xoranth 2y ago
It is the same reason in software sometimes you batch operations: When you add two numbers, the GPU needs to do a lot more stuff besides the addition. If you implemented SIMT by having multiple cores, you would need to do the extra stuff on
20.
by xoranth 2y ago
I believe the author is referring to how many logical threads/hyperthreads can a core run (for AMD and Intel, two. I believe POWER can do 8, Sparc 4). The extra physical registers are there for superscalar execution, not for SMT/h
21.
by xoranth 2y ago
People have engineered solutions to make what is available practical (see all the various quantization schemes that have come out). It is just that there's a limit to how much you can compress the models.
22.
by xoranth 2y ago
Location: Europe, CET timezone Remote: Yes Willing to relocate: Yes (EU/Switzerland) Technologies: C++, Python, Rust, Numpy, Pandas, sklearn, numba, SQL, Rust, Assembly. Résumé/CV: Upon request. Email: d
23.
by xoranth 3y ago
Thanks for the clarification!
24.
by xoranth 3y ago
I believe something like the mechanism you are describing has been in production at Google for at least a decade. See this talk [1]. The kernel interface that the article uses (called sched_ext) is the result of the attempts to mainstream t
25.
by xoranth 3y ago
> * the whole idea hinges on the compiler being able to figure out the correct instruction schedule ahead of time. While feasible for Intel's/HP's in house compiler team, the authors of other toolchains largely did not bot
26.
by xoranth 3y ago
Dumb question. With io_uring, how do you handle lines that straddle between chunks? I'm asking since, AFAIU, the submitted requests are not guaranteed to be completed in order. (The easiest I can think of is submitting reads for "
27.
by xoranth 3y ago
Ok, makes sense. And thanks for the detailed explaination about word boundaries and the hint about the --pcre flag (I hadn't realized it existed).
28.
by xoranth 3y ago
> Also, \< and \> are in ripgrep 14 Isn't that inconsistent with the way Perl's regex syntax was designed? In Perl's syntax an escaped non-ASCII character is always a literal [^1], and that is guaranteed not to chang
29.
by xoranth 3y ago
What GCC is doing at -O3 is encoding even (resp. odd) numbers in a bitmap. 43690 = 0xAAAA = 0b1010101010101010 21845 = 0x5555 = 0b0101010101010101 Then sal rax, cl test eax, 43690 jne .L3 // .L3 m
30.
by xoranth 3y ago
Clang is able to convert the code to a jump table, though GCC can't. https://c.godbolt.org/z/Wq65j4rrM > What would it take to make the compiler optimize this code meaningfully? To make GCC compile the code mea

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