volta83

7 ms·

1.
by volta83 5y ago
This might be an error on both sides. They want to study how websites handle GDPR and CCPA, and that's probably what they submitted. The IRB reasoned that "websites are not people", which is true, but failed to reason that &q
2.
Homegrown Rendering with Rust (Embark Studios)(medium.com)
2 points by volta83 5y ago|0 comments
3.
by volta83 5y ago
A simple way to do this is to: MyNestedMaxHeap(T, Ord) = MaxHeap(MaxHeap(T, Ord), Ord) such that when using MyNestedMaxHeap only one Ord type can be passed.
4.
by volta83 5y ago
> You need some way to enforce that the orderings are the _same_ Just require that the Ord type is the same for all heaps ? MaxHeap(MaxHeap(T, MyOrd), MyOrd) uses the same ordering, but MaxHeap(MaxHeap(T, Ord0), Ord1) does not.
5.
by volta83 5y ago
> If you didn't have canonical implementations, you would have to give up being able to write safe & efficient data-structures like this. No? Just make the type generic on the ordering. Instead of MaxHeap(T), make it MaxHeap(T,
6.
by volta83 5y ago
I agree with you, which is why I don't really understand what the point of improving FP64 perf by 4x is, if that is not the bottleneck for many apps. Per node, a 4x MI250X node has more or less the same BW as a DGX-A100 (8x A100). It h
7.
by volta83 5y ago
Makes sense. Comparing nodes with 2x or 4x MI250X vs 4x or 8x A100-80 it doesn't really seem that there is any speed up at all for memory bound apps.
8.
by volta83 5y ago
Then you must be extremely bad at rust.
9.
by volta83 5y ago
Many in the core team don’t code, don’t even know Rust well, etc.
10.
by volta83 5y ago
I wonder how they manage to keep the FP64 units busy. Seems this is an HPC product, but many HPC apps are memory bound. So to improve FP64 perf by 4 one might need to improve DRAM bandwidth by 8-16x. Otherwise the units would only be stall
11.
by volta83 5y ago
Ideally it would be a constitutional ammendent, stating that privacy is a right of every citizen, and a human right. Legislation to the right to encryption would then just follow from it, but having it in the constitution would make it hard
12.
by volta83 5y ago
Its not completely unrelated. Excess mortality is the only fact that we know for sure given that every country counts "COVID deaths" differently. Given that there is a statistical difference, the only thing we can probably know fo
13.
by volta83 5y ago
Right, but all architectures can handle many combinations of instructions in 1 cycle, so this is not really a great proxy for that. Same for code size. If the instructions are half the size, having 1.5x more instructions still means smaller
14.
by volta83 5y ago
8x 2 byte instructions (16 bytes) lead to smaller code than 4x 8 byte instructions (32 bytes). Counting number of instructions isn't really a good metric for that either.
15.
by volta83 5y ago
> DPU SmartNICs, Which other companies beyond NVIDIA sell DPUs ?
16.
by volta83 5y ago
I just showed the data, and summarized that according to the data, people in the EU had better chances. I never claimed that this data is the result of COVID policies. This is something you made up, and then proceeded to debunk, which is es
17.
by volta83 5y ago
The US didn't act as one entity either.
18.
by volta83 5y ago
Can you change the "shape of the vectors? e.g. 1x16 vs 4x4 to support vectors and matrices?
19.
by volta83 5y ago
> RISC-V is faster.. I find it funny that you make the same pitfall than the author did. Faster on which CPU? The author doesn't measure on any CPU, so here there are dozens of people hypothesizing whether fusion happens or not, and
20.
by volta83 5y ago
The CPU executes the two (or more) dependent instructions "as if" they were one, e.g., in 1 cycle. The CPU has a frontend, which has a decoder, which is the part that "reads" the program instructions. When it "sees&
21.
by volta83 5y ago
Good question. Excess mortality in the USA and the EU in 2020 were ~470k and ~580k deaths. The population of the USA and the EU in Jan 2020 was ~329 and ~447 million. The excess mortality in the USA and the EU in 2020 was ~143 vs ~129 exces
22.
by volta83 5y ago
Running on soft cores.
23.
by volta83 5y ago
You start with BLAS being a factor 2 off, and then go to PETSc, and are another couples of factors off, and then the actual app the scientist wrote, which many use all of the above and the kitchen sink, where every piece and the pieces they
24.
by volta83 5y ago
I think that right now, there is sufficient motivation to implement enough of this to be able to try it out, and then see how it actually behaves in practice. But Rust works on a really wide range of kinds of processors - CPUs, GPUs, FPGAs
25.
by volta83 5y ago
You mean "multi-return" functions? https://github.com/bytecodealliance/wasmtime/issues/1057 We have looked at these before. Modern CPUs have a RAS, and you dont want to mess with that. But there are
26.
by volta83 5y ago
Yeah, one in which AMD actually ended up bankrupt and Intel became the only vendor supplying x86 chips.
27.
by volta83 5y ago
Works is step 0. Works efficiently is step 10000. x86 is at step 10000, ARM at step 5000, power is at step 0. Firefox "worked" before this post on power. Now somebody put enough effort to actually make it usable. The fact that you
28.
by volta83 5y ago
- Have you ever, e.g., computed the sinus of a floating point number in C (sinf) ? - Have you ever multiplied a matrix with a vector, or a matrix with a matrix (GEMM) using BLAS? - Have you ever done an FFT ? - Have you used C++ barriers? O
29.
by volta83 5y ago
How many smartphones using POWERs do you know? Or IoT devices? Or... Or...
30.
by volta83 5y ago
An ISA is like a platform. It is valuable only if it has many users, e.g., application code, optimized for the ISA. HW's job is to then run that code with good perf/cost. OpenPOWER has little software. ARM has a lot of software.

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