tsmi

6 ms·

1.
by tsmi 4y ago
I do totally agree with the comment, and even upvoted it, but in some sense an HDL does 'want to be procedural'. For example: Procedure to make brick wall: For brick in wheel-barrow do To brick, apply mortar, place i
2.
by tsmi 4y ago
> The main point of verilog is to simulate digital logic I disagree. A HDL, which verilog is an instance of, provides a precise description of a digital machine. Once you have that description, many things can be done with it. For exam
3.
by tsmi 4y ago
That’s not exactly the right way to think about it. In HDL, you’re writing an algorithm, but the algorithm produces a physical device, not a computation. It’s like programming a machine to make a watch. At the end you have a watch. Would
4.
by tsmi 4y ago
Modern OoO CPUs solve the need for more physical registers than logic registers with renaming. https://docs.boom-core.org/en/latest/sections/rename-stage.h...
5.
by tsmi 4y ago
One advantage of SkyWater opening its PDK is Universities are starting to back fill all the hardware that is missing. Here's a SerDes from Purdue. I don't think this particular design has been validated in silicon yet though. ht
6.
by tsmi 4y ago
Gotcha. Did you run into any issues with yosys given that it has limited system verilog support? Ibex needed to add a pass with sv2v https://github.com/lowRISC/ibex/tree/master/syn
7.
by tsmi 4y ago
> you will need exact "-mcpu" for decent performance For some definitions of decent, I think that ship has sailed. https://clang.llvm.org/docs/CrossCompilation.html -target <triple> The triple has th
8.
by tsmi 4y ago
I personally am not into the verilog specific books. For me HDLs are hardware description languages, so first you learn to design digital hardware, then you learn to describe them. For that I highly recommend: https://www.cambri
9.
by tsmi 4y ago
Have you considered making an ASIC of your design? https://efabless.com/open_shuttle_program
10.
by tsmi 4y ago
If you're at the point in your career where you're not sure which is the right textbook then "A Quantitative Approach" is likely to be really tough to get through. Computer Organization and Design, by the same authors, i
11.
by tsmi 4y ago
I only brought up the binary size thing to give a concrete example based off the article and the parent's comment. I am totally sure the situation is fluid and changing. My high level point is: changes in "objective measurement&q
12.
by tsmi 4y ago
It's not so much "tricks" that one needs to look out for. The compiler has just tons of internal heuristics on when and when not to apply various code transformations. Those heuristics, first off may not even be applicable f
13.
by tsmi 4y ago
I’m sure that’s what the team that invented segment registers said too. The question is does it make sense to add these to the ISA long term? In the short term, given die density and how memory works today, it has advantages. But die dens
14.
by tsmi 4y ago
I agree mostly with Keller's take but I think he left of one key factor, the quality of the software tool chain. The x86 tool chains are amazing. They're practically black magic in the kinds of optimizations they can do. Honestl
15.
by tsmi 4y ago
Instruction byte count matters quite a lot when you're buying ROM in volume. And today, the main commercial battleground for RISCV is in the microcontroller space where people care about these things.
16.
by tsmi 4y ago
People argue over these minimal differences for good reasons. If <insert objective measurement> = binary size, and I'm buying ROM in volume to hold that binary, +10% ROM address space can easily cost more than the ARM license. Th