tryp

5 ms·

1.
On Gravel(scopeofwork.net)
1 points by tryp 3y ago|1 comments
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by tryp 3y ago
I found this an interesting look into The US Forestry service's philosophy of road management through the lens of Washington State's Olympic National Forest. "The Forest Service – a branch of the Department of Agriculture who
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by tryp 5y ago
Some folks are just not TradeMarksters. They'll teach you that Intel makes processors that implement x86 and amd64 instruction sets. You can Google things on DuckDuckGo. They'll blow their nose on the Kleenex that they bought from
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by tryp 5y ago
BIOS is often able to set mask bits in the CPU or chipset's pci bridges that prevent the devices from being reported to the OS. Before loading additional code like user DXEs or bootloader, BIOS commands a one-way sealing operation that
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by tryp 7y ago
I love that the instruction decode unit's ability to command a flush on branch mispredicts is represented in the diagram as a toilet.
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by tryp 9y ago
As a longtime browser of cross-referenced source generated by LXR [0] I found this article on their new implementation of the backend interesting. [0] http://elixir.free-electrons.com/linux/latest/source
7.
Elixir Cross Referencer: new way to browse kernel sources(free-electrons.com)
1 points by tryp 9y ago|1 comments
8.
by tryp 10y ago
The researchers' writeup, in a very fun form, can be found at https://rol.im/securegoldenkeyboot/ With text as follows for those whom the joviality of the original presentation is undesirable: irc.rol.im #rtchurch
9.
by tryp 11y ago
Toward the end of that slide deck, in the "Slowing Brute Force" section, there the following slide: > Argon2 ensures that both defenders and attackers hash passwords on the same platform (x86) Do they simply mean that currently
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by tryp 11y ago
It actually resides in the pch. The processor is called the management engine. In newer platforms, it gets to decide if the processor even gets to see the bios executable code.
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by tryp 11y ago
I couldn't find much data on the Curie module, but it looks like the only pins required are power and slow io, so I can't imagine it's a super dense bga or anything. Even on the high end Intel socs with over 1k balls a good d
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by tryp 11y ago
A few years ago I implemented the storage system for a special-purpose diagnostic camera. The specification defined (very long) filenames for the saved images using a timestamp and some other data. I used a mostly off-the-shelf microcontrol
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by tryp 12y ago
I'm not sure which ones you're referring to, but the NVDIMMs I'm familiar with [0] are are normal DRAMs with an additional hold-up supercap, controller, and flash. When power goes away, the controller streams DRAM contents t
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by tryp 12y ago
Of course the firmware could hash itself. The question is what value is there in trusting and untrusted component to tell you it's trustworthy.
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by tryp 12y ago
>Why can't the HDD vendors publish a md5/sha1 hash of the firmware so we know what the value should be? Because the only way to actually verify the hash of the firmware is to connect to the drive's controller outside of th
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by tryp 12y ago
The most likely explanation is that 64Mb (8MB) was the highest density part available in the footprint (SOIC-8?) at the time of manufacture and was priced at a significant premium to the 32Mb part.
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by tryp 12y ago
By mundane coincidence, I discovered uefi-firmware-parser yesterday. Along with a radare2 session, it made it much easier to find a null-pointer dereference in an Intel FSP binary blob.
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by tryp 12y ago
(U)EFI is essentially a little OS that eventually loads the OS that runs the software you care about. Intel sponsors most of the core OS code (mirrored) at: https://github.com/tianocore/edk2 A Bios vendor takes that co
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by tryp 12y ago
The best place to look is probably Coreboot. It's the boot firmware used by Google Chromebooks. (Github mirror links used here for politeness to the project's servers.) Taking Intel Haswell processors as an example (because I know
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by tryp 12y ago
An invalid or debug instruction causes the processor to throw an exception and jump to a specific address where "handler" code should exist. This is managed by the OS, so in this case, the OS would look up the proper thing to do a
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by tryp 12y ago
There is typically only one (or a small set) of hardware instruction pointer breakpoints. Every time the CPU is about to execute an instruction, it compares IP to the IP breakpoint register (or set of registers) and if they match, a debug e
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by tryp 12y ago
To be a bit more explicit, using a separate httpd and application server allows a division of labor between the resource-bound task of handling the request + building the response from the network-bound task of dibbling bytes back to the or
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by tryp 12y ago
dmesg output mentions Armada XP pinctrl and xor engine too.
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by tryp 12y ago
I totally agree about micros. They are wonderfully nice and tidy for small, well defined problems. I've had extremely satisfying success using them for communications glue, motor controllers and thermoelectric cooler controllers. I&#x2
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by tryp 12y ago
I am truly excited that there is a push to popularize FPGAs. They often allow a fundamentally different approach to problems and afford a massive improvement in efficiency and flexibility when applied to a given task. This book is a very ap
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by tryp 12y ago
Modern DDR2 SDRAM busses are a bit more involved. They use the address lines as a command word for putting the chips in the correct "link trainging" mode at startup, selecting burst access lengths, enabling self-refresh mode, sett
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by tryp 12y ago
One point to consider is that this algorithm appears to rely on a double-precision floating-point divide at its core, so the speediness measured on a Xeon E5 may not translate to speediness on architectures with weaker floating point units.
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by tryp 12y ago
Also, most current DDR3 controllers "scramble" which wire carries which bit based on the address. The idea is that when writing constant repeating data patterns, spreading energy among the wires reduces emitted EMI. When you do a
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by tryp 12y ago
x
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by tryp 12y ago
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