trynumber9

6 ms·

1.
by trynumber9 21d ago
CAD vs USD is rather stable, varying between 0.70-0.73 the last 12 months though trending down from 0.8 in the last 60 months.
2.
by trynumber9 24d ago
There is a nuance: Xiaomi is not Huawei. They were not sanctioned. This chip is made in Taiwan like all the non-Samsung competition.
3.
by trynumber9 24d ago
In this case it's more that multiple companies (Apple, Qualcomm, MediaTek and now Xiaomi) have used the same process (N3P) to produce multiple chips with similar performance. Regardless of Moore's Law death that isn't surpris
4.
by trynumber9 24d ago
Xiaomi has not been sanctioned like Huawei. So it is made by TSMC on N3P. The Huawei chips, made by SMIC, are so far behind they're not competitive at all with even Xiaomi's first generation chip.
5.
by trynumber9 24d ago
It's an ARM-designed CPU core, made in Taiwan. Very little difference from say MediaTek's upcoming Dimensity SoC just announced earlier because it is made on TSMC N3P instead of N2. I don't think they have any angle with that
6.
by trynumber9 1mo ago
Memory prices are cyclical. But this is bigger and longer than most cycles.
7.
by trynumber9 3mo ago
I guess they don't bother using Speedtest in Switzerland, as the average speed seems about the same as the US: https://www.speedtest.net/global-index Must be a sampling bias or something.
8.
by trynumber9 3mo ago
AMD's first Athlon chips did not run particularily hot. They needed a fan, just like Williamette chips, but actually used less power than the competition. The difference was they had no internal, on-chip diode. If the heatsink and fan
9.
by trynumber9 3mo ago
The plan doesn't involve running fabs again. Too expensive. IBM licenses their manufacturing technology (so far to Rapidus in Japan).
10.
by trynumber9 3mo ago
No, it stems from a lineage of Tegra chips that pre-date the M-Series. This chip was called GB10. One of its predecessors, GV10 was shipped in 2018. It was a 256 bit, unified-memory system on a chip with a Volta GPU and 12 ARM Cores. GB10
11.
by trynumber9 4mo ago
MediaTek designed X925 + A725 CPU. It's already been benchmarked in the GB10 products. It is not even close. Like 0.75x SPECint 2017 of the M5.
12.
by trynumber9 4mo ago
It's the same configuration as GB10. 20 core MediaTek 3nm part which is competitive with a AMD's 2025 16 core 4nm part with similar power draw. https://www.servethehome.com/wp-content/uploads/2026/05
13.
by trynumber9 4mo ago
What's the real cause of them being unable to price competitively? Is it DRAM, NAND flash storage, SoC cost, simply scale?
14.
by trynumber9 4mo ago
I must also admit to preferring Sim City 3000 over 4. I don't know if I can handle a 4K user interface without a magnifier, however.
15.
by trynumber9 4mo ago
I suspect general attitude to AI will split along those who had to apply for jobs in the post-AI world of automatic resume generation and filtering and those who didn't.
16.
by trynumber9 4mo ago
There's little reason at this price. I run both, Plex for people who are already used to it, and Jellyfin for myself and anyone new. At around ~$100 I think the Plex experience was better enough to justify it, personally.
17.
by trynumber9 5mo ago
Nethack embeds Lua 5.4.8, so you don't need it installed from a distribution's package manager. As long as your system can build C99* it can build Lua. And given that Nethack 5.0.0 is C99, this dependency is not reducing portabili
18.
by trynumber9 5mo ago
@jasoneckert For the sake of science, can you disable your e cores and try this test again?
19.
by trynumber9 6mo ago
Question: do those vectorize code as in the example here? I was of the understanding they performed a more limited subset of optimizations.
20.
by trynumber9 6mo ago
Some instructions are microcoded but others take the fast path and avoid the microcode sequencer. Can't patch the latter in microcode RAM.
21.
by trynumber9 6mo ago
It does not. For any of the dual CCD parts AMD has ever released for consumers. Even Strix Halo which has higher bandwidth, lower latency interconnect doesn't make a single L3 across CCDs. It'll probably only happen when they have
22.
by trynumber9 6mo ago
Per compute die it functions as one 96M L3 with uniform latency. It is 4 cycles more latency than the configuration with smaller 32M L3. But there are two compute dies, each with their own L3. And like the 9950X coherency between these two
23.
by trynumber9 6mo ago
> 16MB L2 (8MB per die?) It is indeed 8MB per compute die but really 1MB per core. Not shared among the entire CCD.
24.
by trynumber9 6mo ago
So do you have a lot of trust in people that "cannot hope of ever achieving a comfortable life"? It seems like a risky proposition.
25.
by trynumber9 6mo ago
>And the government did nothing. Why didn't a private investment company, even venture capital, extend them a bridge loan? It seems like the type of technology that could have decent returns in licensing fees. I ask this question be
26.
by trynumber9 6mo ago
Unfortunately Apple is learning to be as annoying too. I don't want to upgrade to Tahoe which is inscrutable to me. Maybe remind me next year. But they pop up every week reminding me to "upgrade" even though most the problems
27.
by trynumber9 6mo ago
"Mainly" but they've been assaulting Russian boats and ships with USVs and submersibles. For example - https://en.wikipedia.org/wiki/Sea_Baby#Sub_Sea_Baby
28.
by trynumber9 8mo ago
No. It's trying to analyze the CPU core but clarifies the device under test as that may have performance implications. There is cooling and possibly manufactured configured power limits.
29.
by trynumber9 8mo ago
It's $2000
30.
by trynumber9 8mo ago
What resolution is that display?

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