smprather

8 ms·

1.
by smprather 1mo ago
I encourage you to try, but honestly, with almore 30 years experience making chips, I would still classify this puzzle as "pretty damn hard".
2.
by smprather 1mo ago
That would have added a definite layer of complexity, but really just a token/cpu drain on the puzzle solver. Had they done that, I would have had Claude write a "gds matcher" that took the gds files of the sky std-cell lib,
3.
by smprather 1mo ago
The Last Starfighter :).
4.
by smprather 1mo ago
Nope. I work at Cadence and literally have free access to every one of our tools, but I didn't use a single one of them to solve the puzzle.
5.
by smprather 1mo ago
No need for Calibre. Me + KLayout + Claude had a verilog sim of the example vcd input and gate-level netlist 30 minutes after I cloned the repo.
6.
by smprather 1mo ago
Solved it. Took me ~6 human hours, over a total of 24 hours. But it was NOT easy! I've been making chips for amost 30 years, and I run the https://github.com/smprather/engineering-loadout project, so I had all the
7.
by smprather 2y ago
I clicked link expecting the likes of Defender and Joust. Nope.
8.
by smprather 4y ago
I'm not even a "car guy" but I sure would love to have one of those GT40's from Ford vs. Ferrari. (With a working door :))
9.
by smprather 5y ago
They now have a mostly functional interpreter. This should turbo-charge tight write/test/write/test loops. I wish I would have had it when I wrote my last mid-sized Crystal project.
10.
by smprather 6y ago
You wrote an event driven simulator. We use Verilog simulators in my industry. http://iverilog.icarus.com/
11.
by smprather 6y ago
Looks like some people are trying to re-create it at least. https://github.com/srg320/FpgaSnes
12.
by smprather 6y ago
Has Nintendo released officially, or leaked, the RTL for any of the processors in the SNES? If someone could get their hands on that, then the emulation authors should be able to achieve perfection.