shetaye

5 ms·

1.
by shetaye 8mo ago
I assume the idea is to have the entire constellation be the data center in question. Laser back haul transceiver bandwidth is in the same order of magnitude of rack-to-rack bandwidths [1][2]. I could see each sat being a rack and the entir
2.
Theseus - Train like a foundation lab(github.com)
1 points by shetaye 8mo ago|0 comments
3.
by shetaye 8mo ago
Interesting, the protocol seems to assume symmetrical performance i.e. X-...->Y and Y-...->X will have the same latency so long as they follow the same path?
4.
by shetaye 8mo ago
Very interesting! Nice work on your thesis. I am curious: if the data is not resident on the GPU (e.g. multi-TB datasets, line-rate packet inspection, etc.), is this approached bottle necked by the PCIe bus? (You may have addressed this i
5.
by shetaye 9mo ago
The CPU baseline seems to be the beefy host CPU. The AIE is presumably faster than what you could do with the FPGA (DPS, LUT, etc.) alone.
6.
by shetaye 9mo ago
There also exists cuda-gdb[1], a first-party GDB for NVIDIA's CUDA. I've found it to be pretty good. Since CUDA uses a threading model, it works well with the GDB thread ergonomics (though you can only single-step at the warp gran
7.
by shetaye 10mo ago
True, but unfortunately the response from Stanford has been to introduce triple and quad rooms ;) This is not entirely their fault. Stanford is subject to Santa Clara County building regulations, and those tend not to be friendly to large u
8.
by shetaye 10mo ago
I agree in that freshmen should get the "experience" at least once. However, the way Stanford has arranged housing has meant that a good number of students will not live in a single for any of their 4 years.
9.
by shetaye 10mo ago
Regarding Stanford specifically, I did not see the number broken down by academic or residential disability (in the underlying Atlantic article). This is relevant, because > Some students get approved for housing accommodations, includin
10.
by shetaye 11mo ago
Great read! I'm sure expensive enterprise tooling exists for busy kitchens to manage safety protocols (or not?), so it is very cool to see high quality tooling for this kind of thing out in the open. After watching so many Chubby Emu v
11.
Thoughtbubbles: An Unsupervised Method for Parallel Thinking in Latent Space(arxiv.org)
4 points by shetaye 1y ago|1 comments
12.
by shetaye 1y ago
Agreed! The gulf between pure-C++ CUDA and PTX is getting larger with these optimizations. My understanding is that Deepseek used PTX instructions that either had no corresponding C++ implemented (like `wgmma` mentioned in the article) or u
13.
by shetaye 1y ago
Arguably the OS includes the entire distribution, not just the kernel. MacOS ships the window server and the entire graphics stack, so the GUI is certainly part of MacOS, and so at least some OSes include a GUI.
14.
by shetaye 1y ago
If you are still interested in SMP on a 64-bit ARM, we have had some success with virtual memory/cache/peripherals on the Pi Zero 2 W
15.
by shetaye 1y ago
You absolutely can, and should! :)
16.
by shetaye 1y ago
There aren't any 1hr+ lectures, just some readings (selected from the manuals in `docs/`) and a bit of exposition from the professor before diving into the lab. Lots of "as needed" assistance
17.
by shetaye 1y ago
IMO this is kind of the tradeoff. In 140E we do touch on virtual memory (w/ coherency handling on our specific ARM core), FAT32 "from scratch", etc. but it comes at the expense of prerequisites. There is a lot of effort to
18.
by shetaye 1y ago
People interested in a "read the manual and code it up on real hardware"-type guide should take a look at Stanford's CS140E[1] repo! Students write a bare metal OS for a Raspberry Pi Zero W (ARMv6) in a series of labs, and we