scott_wilson46

5 ms·

1.
by scott_wilson46 7y ago
The ASIC flow is way more involved than the FPGA flow, you need to think about all sorts of other things, like what pads you want on your chip, how you are going to generate clocks, floor planning, power distribution, test, and a whole raft
2.
by scott_wilson46 7y ago
In my day job as an FPGA developer I am using totally open source tools for simulation and verification (the only tool we pay for is Vivado but you have to pay for that in order to build for the FPGA). The simulator is icarus verilog and d
3.
by scott_wilson46 7y ago
I disagree about for loops, you actually end up using these quite a lot in vhdl/verilog (with understanding about what logic you are going to end up with), if you want to do the same operation on multiple things: input [NUM_OF_MULT
4.
by scott_wilson46 8y ago
I use it exclusively. I know of other trading firms that use verilator too. To be honest, no matter how big the company, how deep the pockets, theres still going to be a finite amount of questa licenses available. If you use Icarus Veril
5.
by scott_wilson46 8y ago
I use Icarus Verilog at work for a fairly complex trading system on an FPGA so I disagree that FOSS simulators are almost totally useless. It supports most System Verilog features and works well with cocotb. In fact the fact that it’s ope
6.
by scott_wilson46 8y ago
I disagree with this, you don't necessarily need a whole team of people and massive amounts of cash to do FPGA development and you don't necessarily need expensive tools. For my current company I created a complete FPGA based tra
7.
by scott_wilson46 9y ago
I've had a different experience to this. I've worked on ASIC's for over ten years and have had experience with nearly all aspects of the design flow (from RTL all the way to GDS2 at one point or another). I've taped ou
8.
by scott_wilson46 10y ago
I think you can treat 60 - 70% of the FPGA design flow as open source. For example, I am developing a system using PCIe, 10G Base T and some logic to send and receive network packets and to design the HDL and test it, I am using two open s
9.
by scott_wilson46 10y ago
In actual fact for Xilinx based FPGA's this is quite straightforward. An example for 10G Base R: You can get Xilinx's component for their pma/pcs for 10g base-r ethernet for free from vivado and stick one of the macs from op
10.
by scott_wilson46 10y ago
I've heard (although admittedly never seen in practice) that some places take a long time for this sort of things (running over a cluster of computers overnight). If you could do the same job on a single F1 instance in say an hour the
11.
by scott_wilson46 10y ago
Xilinx provide software drivers and IP for PCIe DMA and memory mapped interfaces. These are fairly easy to integrate (probably not the best for latency though - I've developed my own but I require a specific use case - low latency but
12.
by scott_wilson46 10y ago
Nowadays, I don't believe you need a paid-for simulator like Questa, VCS, etc. I am developing verilog in my day job for FPGA's using icarus verilog (an open source simulator)which works fine for fairly large real world designs (
13.
by scott_wilson46 10y ago
Monte Carlo sims for options pricing? I've done this before on FPGA, might have a go at doing it for this instance as a fun exercise to test the concept!
14.
by scott_wilson46 10y ago
This all seems highly sensible advice to me!
15.
by scott_wilson46 11y ago
It should be possible to write the majority of the code for an FPGA in a generic fashion and get the tools to infer things like RAM's by the way the Verilog or VHDL is written. Ideally, I think you should only have FPGA specific block
16.
by scott_wilson46 11y ago
Actually the IC design tools are a lot more expensive than 50k to 100k. You need a variety of tools for a modern process node (Calibre being one of them usually used for LVS/DRV - checing the GDS2 against the schematic and checking th
17.
by scott_wilson46 11y ago
In fact some of the Stratix 10 FPGAs have over 9 Teraflops...
18.
by scott_wilson46 11y ago
I think this is a common misconception in the debate about GPU's vs FPGAs. If you take a top of the range GPU you get 2.7 Teraflops of performance (according to the GTP Titan review I just looked at: http://www.techspot.co
19.
by scott_wilson46 12y ago
I think if you can crack the modelling and simulation of asynchronous clock domains then I suspect you will have something that the other HLS solutions don't have at the moment that would be an incredibly useful feature. Design with a
20.
by scott_wilson46 12y ago
If you are interested in using python for unit testing there is also Cocotb which is a python based library for running verilog and vhdl simulations. It interfaces to the simulator and allows you to stimulate your design directly from pyt
21.
by scott_wilson46 12y ago
Actually another thing I am curious about is how asynchronous clock domains are handled Usually this is something thats quite tricky to model in a HLS tool. Also, how about simulating the interactions between the domains?
22.
by scott_wilson46 12y ago
I can't help but feel that the VHDL that was written is a bit overly verbose. You could probably write something like: i_sm: process(clk, reset) begin if (reset) then state <= DATA_BITS; elsif (clk'event an
23.
by scott_wilson46 12y ago
f you are interested. I did something similar for fpga: https://github.com/scottwilson46/FPGARandom
24.
by scott_wilson46 12y ago
Theres also the SocKit from arrow: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=E... Very similar to Zynq but from altera rather than xilinx
25.
Mercenne Twister FPGA implementation on GitHub(scottwilson46.github.io)
1 points by scott_wilson46 12y ago|0 comments
26.
Random Numbers on FPGA (running monte carlo sims on FPGA)(scottwilson46.github.io)
1 points by scott_wilson46 12y ago|0 comments
27.
by scott_wilson46 12y ago
It's not going to limit clock speed, its just not going to work. To write multiple values to different ram locations (considering a ram has at most two ports) would require you to stay in the INIT state for 9 cycles and do something l
28.
by scott_wilson46 13y ago
One thing to note is that if as the paper says: "Many well-known web-sites deploy distributed in- memory caches, which are implemented with standard DRAM on a large array of x86 servers, to reduce access load on databases" then a
29.
by scott_wilson46 13y ago
Any modern ASIC being built would be tested using Automatic Test Pattern Generation. This involves connecting all the registers in the chip into a chain and feeding patterns in and out of the chains and stimulating the logic between regist