santaboom

7 ms·

1.
by santaboom 21d ago
Op mentions that server side sync occurs outside of 200ms card/reader interaction.
2.
by santaboom 2mo ago
found this: https://logicaffeine.com/guide
3.
by santaboom 7mo ago
Yes, bandwidth within a chip is much higher than on a bus.
4.
by santaboom 1y ago
Lol get out of the echo chamber Edit: to make this helpful, look at Broadcomm interconnect, switching technology, copackaged optics
5.
by santaboom 1y ago
See figure 1 in [0] operation execution is just 0.1pj of 70pj required for a 32 bit int addition… how do you think I was applying amdahls law? Edit: I was using amdahls law as it applies to parallel processors. However in terms of energy
6.
by santaboom 1y ago
Perhaps instead you are referring to the program graphs and whether they are better represented as hyper graphs [0] with certain regular edges within a 2D layer and hyper edges between 2D layers? If so, good question and I am not sure if t
7.
by santaboom 1y ago
Curios what you mean by 3D and also how 3D is used. Assuming something like [0] I can pretty confidently tell you that it is not 3D as it is a low power microcontroller and this technology is mostly used in large expensive HPC/AI chips
8.
by santaboom 1y ago
See amdahls law Edit: [0] https://en.m.wikipedia.org/wiki/Amdahl%27s_law
9.
by santaboom 1y ago
All very informative, I had some quibbles. While it is true that cheap and expensive FPGAs exist, an FPGA system to replace TPU would not use a $0.50 or even $100 FPGA it would use a Versal or Ultrascale+ FPGA that costs thousands, compared
10.
by santaboom 1y ago
Good questions, below I attempt to respond to each point then wrap it up. TLDR: even if TPU is good (and it is good for Google) it wouldn’t be “almost as good a business as every other part of their company” because the value add isn’t FROM
11.
by santaboom 1y ago
Not sure what you mean. Who do you think fabs broadcomm and google chips