rnrn

6 ms·

1.
by rnrn 1mo ago
Which model wrote this bizarre article? Lots of emphasis on no kernels written and nothing recompiled but the intro and conclusion somehow suggest this is also the value of runinfra’s agents the rewrite software ? Walk through the theory of
2.
by rnrn 2mo ago
looks like a bunch of boring desks for software developers, i don't see any electrical or computer engineers
3.
by rnrn 6mo ago
> For example, they invented the .eh_frame walking technique to get stack traces from binaries without frame pointers enabled. This is not an accurate summary of what they developed. Using .eh_frame to unwind stacks without frame pointer
4.
by rnrn 6mo ago
No, wrong decade and wrong split - the test & measurement equipment and scientific equipment was long gone from HP at the time of the HP -> HP inc + HPE split. It ended up in Agilent (1999) and from there Keysight. HP semiconductors
5.
by rnrn 6mo ago
How do get the weights for the right set of experts for a given batch of tokens into fast memory at the right time? The activated experts is only available after routing, at which point you need the weights immediately and will have very po
6.
by rnrn 6mo ago
Why is there a new kernel driver here at all? It appears that all it does it allocate system RAM (“DDR4”) and export it as a dmabuf for import to cuda as mapped external memory. Then a userspace shim hijacks APIs to use that if gpu memory i
7.
by rnrn 9mo ago
This is not about reclaiming memory by swapping the contents out to disk. It is about killing processes due to having overcommitted beyond the available memory plus swap space. The processes thrown out of the plane (targeted by the OOM kill
8.
by rnrn 11mo ago
It’s not a cargo cult if the actions directly cause cargo to arrive based on well understood mechanics. Regardless of whether it would be better in some situations to align to 128 bytes, 64 bytes really is the cache line size on all common
9.
by rnrn 11mo ago
> even on x86 on recent server CPUs, cache-coherency protocols may be operating at a different granularity than the cache line size. A typical case with new Intel server CPUs is operating at the granularity of 2 consecutive cache lines I
10.
by rnrn 1y ago
Do you use some old version of iTunes to put music on it or are there other tools with better support for old iPods?
11.
by rnrn 1y ago
This was in the “truth” posted by Trump on his social media announcing the deal: > It is my Great Honor to report that the United States of America now fully owns and controls 10% of INTEL, a Great American Company that has an even more
12.
by rnrn 1y ago
Are you sure congress didn’t authorize this ? i.e. actually specified that the money could only be used for grants and could not be used for equity purchases? > The Department of Commerce is authorized to provide funding in various forms
13.
by rnrn 1y ago
I thought this too, but after reading some of the other comments here I read some of the text of the chips act and the 2021 NDAA (mostly section 9902) and AFAICT Congress appropriated a bunch of money for financial assistance for semiconduc
14.
by rnrn 1y ago
*consummate Vs
15.
by rnrn 1y ago
> This should be made obvious by the fact that both the metal-semiconductor transistor (i.e. MESFET, patent filed on 1925-10-22) and the depletion-mode metal-insulator-semiconductor transistor (i.e. depletion-mode MOSFET, patent filed on
16.
by rnrn 1y ago
> The NMOS transistors used in the 6502 were quite large and worked on the basis of electrostatic charges ... as opposed to bipolar transistors that are inherently quantum in operation Forming a conductive channel in silicon in any FET a
17.
by rnrn 1y ago
Are these instances actually funded by 2021 IIJA BEAD program? I don’t think Illinois has actually awarded any of that funding to providers to build anything yet. It looks like the original schedule was to start awarding grants this summer
18.
by rnrn 1y ago
removing comment since I regret attempting to engage in this thread
19.
by rnrn 1y ago
removing comment since I regret attempting to engage in this thread
20.
by rnrn 1y ago
I think you are confusing uniform registers with the uniform keyword in RSL / GLSL / HLSL? maybe some vendors have had an equivalent to uniform registers for 20 years, but per the articles’ references they are new in nvidia GPUs i
21.
by rnrn 1y ago
I don’t think x86 as an ISA is necessarily declining much and AMD has products with zen4c / zen5c compact cores intended to compete with Arm server products. AMD doesn’t have to pay licensing / royalties for x86 AFAIK and probably
22.
by rnrn 1y ago
I assume the question is why AMD is not making EPYC or Ryzen processors with Arm cores for the application processors. AMD continuing to have the Xilinx line of FPGAs with some Cortex cores and having Arm management cores that run firmware
23.
by rnrn 2y ago
we could also look to magnetoresistance and go for giant, colossal, extraordinary
24.
by rnrn 2y ago
it's too bad vLLM and VLM are taken because it would have been nice to recycle the VLSI solution to describing sizes - get to very large language models and leave it at that.
25.
by rnrn 2y ago
a full duct spinning at 10k rpm seems like it would massively increase stress on the blades
26.
by rnrn 2y ago
> It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate. in theory only. caravel had hold time violations and the pin configuration mostly didn’t work for the
27.
by rnrn 2y ago
Since i posted https://news.ycombinator.com/item?id=43124176 , they have revised again to acknowledge that many of the other generated kernels are also broken: > Furthermore, we find the system could also find other novel
28.
by rnrn 2y ago
As I write this (after the updates to the evaluation code), https://pub.sakana.ai/ai-cuda-engineer/kernel/2/23/optimize-... is on their top of their list of speedups, with a claim of 128x speed up on a f
29.
by rnrn 2y ago
Answer: it can’t. The author has updated the post with corrected AVX measurements, with the original ~340 GB/s revised down to 31.7 GB/s. (Thanks CowFreedom)
30.
by rnrn 2y ago
> But about bandwidth, matrix multiplications happen mostly in cache and that has a lot more bandwidth than RAM. Blocks of the matrix are loaded to cache (explicitly in CUDA) and used multiple times there. The post is about dot product,

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