rigtorp

6 ms·

1.
by rigtorp 2mo ago
You would use one of those approaches: If you align and pad each slot there won't be any false sharing and the stream prefetcher can kick in if there's only one producer or consumer. If you use bijective hashing you reduce false s
2.
by rigtorp 2mo ago
Here's my widely used implementation of this approach in C++: https://github.com/rigtorp/MPMCQueue
3.
by rigtorp 2mo ago
That looks like a rewrite of my earlier work: https://rigtorp.se/ringbuffer/
4.
by rigtorp 9mo ago
Better to use the Gmail API to incrementally backup your mail: https://github.com/rigtorp/gmbackup
5.
by rigtorp 9mo ago
I have a tool that saves each mail as a single file using the Gmail API: https://github.com/rigtorp/gmbackup
6.
by rigtorp 1y ago
Interesting, of course many computations can be expressed as a graph. In the case of the bipartite graph we perform belief propagation on to decode LDPC where is the optimization from the distributive property? The parity matrix would typic
7.
by rigtorp 1y ago
How is belief propagation used for decoding LDPC codes related to FFT?
8.
by rigtorp 3y ago
I think it will be invalidated due to RFO when the reader reads the write index. Only when multiple readers reads the same cache line without any intervening write will the RFO heuristic be disabled.
9.
by rigtorp 3y ago
It might also be better for performance since the two cores can RFO the buffer pointer cache lines from each other.
10.
by rigtorp 3y ago
There might be an additional optimization in having the writer also cache it's write index on the cache line together with the read index cache. This way the writer would only do writes to the write index cache line. The hardware might
11.
by rigtorp 4y ago
I have something similar but in C++: https://github.com/rigtorp/c2clat
12.
by rigtorp 4y ago
You might need to add -fno-omit-frame-pointer to help ASAN unwind the stack.
13.
by rigtorp 5y ago
You're incorrect, garbage collection would be the biggest problem for that use case. You have to be really careful even with your C/C++ code, warming up the branch predictor between packets etc, see my article for some pitfalls:
14.
by rigtorp 5y ago
The standard says that a thread must eventually terminate, do an atomic operation or do IO. So the while(lock.exchange(true)); loop is different. Also keep in mind that C++11 specifies std::mutex::lock() to have acquire semantics and unlock
15.
by rigtorp 5y ago
There's even more discussion on the lock memory ordering on Stackoverflow: https://stackoverflow.com/questions/61299704/how-c-standard-... Taking a lock only needs to be an acquire operation and a compiler ba
16.
by rigtorp 5y ago
Yes that's right!
17.
by rigtorp 5y ago
Well isn't that just a normal lock/mutex of the "lightweight" type (only enter kernel on contention)? You cannot use that in non-preemptible context.
18.
by rigtorp 5y ago
Deploy to production :). You can use a model checker that understands C++11 memory model.
19.
by rigtorp 5y ago
His rant only applies to preemptible threads. If you don't have preemptible threads spinlocks works great. The linux kernel uses them in non-preemptible contexts.
20.
by rigtorp 5y ago
It's nonsense to do this when you can be preempted. But you can run one thread per core and avoid preemption. You can tune the linux kernel to avoid almost all preemption, due to TLB shootdowns etc: https://rigtorp.se/l
21.
by rigtorp 5y ago
I now think it's actually this part of the standard that prevents it: http://eel.is/c++draft/intro.multithread#intro.progress-7 Basically a compiler can not optimize a non-deadlocking program into a potentially de
22.
by rigtorp 5y ago
Yes this re-ordering can cause a deadlock. But it's not an allowed optimization to change a non-deadlocking program into a potentially deadlocking program, so this reordering can not happen. ( http://eel.is/c++draft&#x2F
23.
by rigtorp 5y ago
I think reitzensteinm was referring to the actual data inside the ring. There is a false sharing problem there particularly for the MPMC type ring buffer like disruptor. The solution is to pad each data slot in addition to the read and writ
24.
by rigtorp 5y ago
You can align and pad each ring buffer slot to the cache line size. Example https://github.com/rigtorp/MPMCQueue/blob/master/include/rig...
25.
by rigtorp 5y ago
Ringbuffers and thread-per-core architecture is great for low latency transaction processing systems, like exchanges and trading systems. Sometimes you don't have time to do things perfectly and might use a spinlock when initializing s
26.
by rigtorp 5y ago
I've written some on this topic. Start here https://rigtorp.se/virtual-memory/ , there is more on similar stuff on my website.
27.
by rigtorp 6y ago
Yes, I've done this using libFuzzer. Supply custom mutation and crossover functions that generates interesting floating point numbers. Then let the coverage guided fuzzer exercise your code. https://rigtorp.se/fuzzing-f
28.
by rigtorp 6y ago
All loads and stores are atomic. I'm also pretty sure ARM has coherent caches. What ARM does allow is for CPUs to optimize the order it loads and stores from cache as opposed to x86 TSO guarantee. DMB barrier instruction on ARM allows
29.
by rigtorp 6y ago
As I understand 'full task-isolation mode' will prevent compaction, completely disable vmstat timer etc. So it provides additional isolation. Since you already switched into kernel mode, might as well deliver a signal to let you k
30.
by rigtorp 6y ago
There was also this recent patch https://lwn.net/Articles/816211/ to deal with kthread affinities. Even with isolcpus I find I still need to run pgrep -P 2 | xargs -i taskset -p -c 0 {} and deal with the workqueue

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