ranma42

5 ms·

1.
by ranma42 3d ago
USB-C actually has pins dedicated to application/debug use (SBU1 and SBU2). "SBU1 and SBU2: these are low-speed lines used only for Alternate Mode and accessory mode. For example, with DisplayPort, AUX+ and AUX– transmit over the
2.
by ranma42 1mo ago
I first encountered Pascal (probably Turbo Pascal) on our Amstrad CPC 464, which being bought as used item came with lots of software floppies including some CPM stuff. Lacking a manual I never really used it though. I do remember it had a
3.
by ranma42 4mo ago
How do you distinguish between input (Keyboard/USB) and output (Browser/Graphics stack) delays in this test?
4.
by ranma42 4mo ago
> No BSP, no kernel source, no vendor documentation — just a DTB extracted from the stock Android firmware and rebuilt from there. Judging from the build.sh, it looks like this is just using unmodified upstream u-boot and tools from the
5.
by ranma42 5mo ago
> The TL-SG108 uses a 4Mbit (512KiB) SPI flash chip from Cfeon, which is too small to contain any assets for a web management interface The https://github.com/logicog/RTLPlayground alternative firmware for RTL8372&#
6.
by ranma42 11mo ago
IIRC ReactOs forbids you from contributing if you had access to the windows source code in some way shape or form.
7.
by ranma42 11mo ago
I've been mounting my 3.5" hard drives on those "fad" rubber band 5.25" drive bay adapters for decades and have not noticed any increased failure rate at all. Sure, seek time may be worse, but the reduced noise has
8.
by ranma42 1y ago
Not OP, but I installed a "Balcony solar" 1.4kWp panels 2.4kWh battery system on my parents garage. The only subsidy was the tax free purchase of the components (we did file for an additional tax break with the city, but they had
9.
by ranma42 1y ago
> you are recommended to get the shingles vaccine instead of the chickenpox vaccine since the way the disease presents and how the body reacts to it changes with age (technically shingles can happen at any age but generally herpes zoster
10.
by ranma42 1y ago
It does say "Certain cough medicines and illicit hallucinogenic substances are also known to trigger it"
11.
by ranma42 1y ago
BTW looking at the 8051 patch bytes, they look like 8051 code to me. 0x02 is the ljmp opcode, so this is a jump table: 0x02, 0x40, 0x58, 0x02, 0x40, 0x4e, 0x02, 0x44, 0x00, 0x02, 0x42, 0x2b, 0x02, 0x41, 0x82 I poked at a vsc73xx-based switc
12.
by ranma42 1y ago
I have the ST one (X-NUCLEO-LPM01A), but its range is actually not enough for something like an ESP32, it goes into "overload" as the max current is 50mA for dynamic (100kHz bandwith) and 200mA for "static" measurements.
13.
by ranma42 1y ago
The partition table listing from the microSD card shown in the video (before installing a custom u-boot/Linux) shows partitions marked as the Linux partition type at least.
14.
by ranma42 1y ago
The amount of power you can dump for balancing is just a fraction of the charge/discharge power (because it only needs to offset differences in self-discharge rate). So you still need a proper dummy load when you want to dump more. Sim
15.
by ranma42 1y ago
> Since there's no point in generating keys for a device which will not be used in Japan, non-Japan SKUs don't have Osaifu-Keitai functionality. So even if you rooted your phone and had full access to the secure element, if you
16.
by ranma42 1y ago
In a similar vein, there is https://aminet.net/package/mus/misc/AlgoMusic2_4u.lha , from ~96 or so.
17.
by ranma42 2y ago
I do actually see the problem that the ESP32 doesn't automatically reconnect to the stronger AP. I think this gets triggered when then stronger AP is briefly unavailable (reboot or radar scan or whatever) and it switches to the weaker
18.
by ranma42 2y ago
> I also upgraded OpenWrt Routers by soldering bigger RAM and bigger flash chips in the past Sadly this is harder than it used to be because with devicetree the flash size is hardcoded, where before it was auto-detected (so previously yo
19.
by ranma42 3y ago
> Pixel (4 or later), or Pixel Watch, Unfortunately I could not get Suica to work on my Pixel 7a, while a fellow traveller with an iPhone had no issue. So AFAICT for Pixels you sadly still need a Japanese device to use Suica in Google Wa
20.
by ranma42 3y ago
Also OpenWRT udev itself is tiny: 20.0K Oct 13 2022 /usr/lib/libudev.so.1 8.0K Dec 15 2022 /sbin/udevtrigger
21.
by ranma42 3y ago
Vodafone in Germany was happy to give me an eSIM for a prepaid plan, not even a store visit required (but it did require taking a photo of my ID and a identity verification video call where someone checks your video against the ID). I guess
22.
by ranma42 3y ago
Athereos wireless cards (ath10k) have also used Xtensa. And the audio DSP in newer intel chipsets (e.g. Apollo Lake) is also Xtensa-based, but unfortunately quite locked down (signed firmware only). See https://thesofproject.gith
23.
by ranma42 3y ago
> Now you might ask, why does the webcam have an endpoint with a 0 byte MaxPacketSize on its first interface? Who knows! This one has a simple answer: USB is a shared bus and limited in bandwidth. Isochronous endpoints transmit continous
24.
by ranma42 4y ago
RK3568 / RK3588 have 3 SATA controllers and for example the Rock Pi 3A seems to have the SATA routed to the bottom m.2 connector, as well as the possibility to switch the USB3 port over to SATA https://linuxgizmos.com/p
25.
by ranma42 4y ago
I think the article in question actually is for older BIOSes that don't have flashback or similar. Instead this relies on the "BIOS Boot Block" still being intact in the flash, so you do need a partially working BIOS flash, C
26.
by ranma42 4y ago
DisplayPort is the more surprising one. DDC came from VGA and DVI and uses the I2C lines that also connect the EDID EEPROM, but Displayport doesn't even have I2C pins if you look at the pinout, so it has to be tunneled: "DisplayPo
27.
by ranma42 4y ago
> 64 registers with 3 registers per instruction would require 21 bits Actually only 18. With 21 bits you can get 128 registers.
28.
by ranma42 4y ago
x64_32 never really took off and there was some discussion of removing the support in the past: https://lwn.net/Articles/774734/
29.
by ranma42 4y ago
For coreboot there are actually some interesting low-level emulation options: The PCH has "I/O Trap" settings, where you can set about 4 ISA I/O ranges to be trapped (generates an SMI, so the SMM code can handle it), so
30.
by ranma42 4y ago
Its just the reference implementation of the EL3 "Secure world" monitor, and this is where some of the power management stuff is implemented according to ARM standards (e.g. PSCI). Technically I'm pretty sure you could do wit

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