pbalcer

6 ms·

1.
by pbalcer 11mo ago
This exists in many parts of the world. And is usually reserved for the ultra wealthy, especially if you want it to be near a big city. One famous example is Karuizawa.
2.
by pbalcer 1y ago
Readable code is code that has empathy for the reader and tries to minimize the cognitive load of interpreting it. That's one of the goals of abstraction layers and design patterns. Yes, it's all subjective, and depends on the rea
3.
by pbalcer 2y ago
You'd be surprised how complex a typical memcpy implementation can get to eke out all the performance out of a platform for all the possible scenarios. And while I agree it might not be considered an algorithm in the strictest sense, i
4.
by pbalcer 2y ago
SteamOS is a much more streamlined console-like experience for gaming. Even things as simple as system updates is far less annoying on Linux/SteamOS than it is on Windows. This is especially important in, for example, a set-top box med
5.
by pbalcer 2y ago
One of the reasons why they can do unified memory efficiently is because the CPU/GPU is a single SoC. If you separate them, you end up with a normal PC architecture, with memory having to go through a PCIe bus. This is possible to do w
6.
by pbalcer 2y ago
Disclaimer: I work on this stuff for Intel At least for Intel, that is just not true. Intel's DPC++ is as open as it gets. It implements a Khronos standard (SYCL), most of the development is happening in public on GitHub, it's per
7.
Intel's Big AI Bet: Gaudi 3 Ft. Supermicro – System Tour, PyTorch, More [video](youtube.com)
2 points by pbalcer 2y ago|0 comments
8.
by pbalcer 2y ago
I've been using Gemini-1.5-Pro-2M through Poe for creating e-book recaps and just generally interactively jogging my memory about a prior entry of a book in a series when a new one comes out. It's been working surprisingly well, e
9.
by pbalcer 2y ago
Is the alternative "mass hacking"? I thought all this software did was check a box on some compliance list. And slow down everyone's work laptop by unnecessarily scanning the same files over and over again.
10.
by pbalcer 2y ago
I'll just leave this here: https://computeexpresslink.org/wp-content/uploads/2023/12/CX... Combined with the fact that Intel created both CXL and Optane, it stands to reason that the plan was to com
11.
by pbalcer 2y ago
Xilinx made triSYCL ( https://github.com/triSYCL/triSYCL ), so maybe there's some chance AMD invests first-class support for SYCL (an open standard from Khronos). That'd be nice. But I don't have much hope
12.
by pbalcer 2y ago
> Qualcomm and other ARM manufacturers creaming them on AI stuff That's mostly on Microsoft's DirectML though. I'm not sure whether AMD's implementation is based on ROCm (doubt it).
13.
by pbalcer 2y ago
These are consumer-grade mobile and laptop chips. That are going into products that won't get sold in the US anyway. Oh, and other Chinese companies, that do sale their products in the US, like Lenovo or Oppo, can get these same chips
14.
by pbalcer 2y ago
I'm gonna go with Occam's razor. There's no real goal here other than political pandering.
15.
by pbalcer 2y ago
> It would require a reverse lookup structure from address to buffer handle, e.g. red-black tree. Maintaining it would no longer be O(1). Not necessarily. If you are able to map a block of normal memory in a known location relative to th
16.
by pbalcer 3y ago
Just curious, how does this work out in terms of TCO (even assuming the price of a Groq LPU is 0$)? What you say makes sense, but I'm wondering how you strike a balance between massive horizontal scaling vs vertical scaling. Sometimes
17.
by pbalcer 3y ago
That's what I have (RX 7900XT on Arch), and ROCm with pytorch has been reasonably stable so far. Certainly more than good enough for my experimentation. Pytorch itself has official support and things are pretty much plug & play.
18.
by pbalcer 3y ago
The reason is physics. NAND just isn't fast enough (and requires firmware wear-leveling, which can mess up latency) for this to be practical.
19.
by pbalcer 3y ago
it's possible to get <1us with Optane PMem (the dimms) in fio, you just need to use the memory-specific engines so that it avoids the fs/block layer.
20.
by pbalcer 3y ago
The point is that on PMem that is simply "sfence", and not a potentially super-expensive "fsync" syscall... Fsync is an fsync, not a memory barrier...
21.
by pbalcer 3y ago
Yup, works just fine. Overall pytorch on ROCm 5.6 has been working very well. I'm impressed with how stable it is, given how much hate AMD driver stack has been getting.
22.
by pbalcer 3y ago
On my machine with AMD RX 7900XT, it takes ~0.17s per image. Are you using SD Turbo Scheduler node?
23.
Nvidia Shows Intel Gaudi2 Is 4x Better Performance per Dollar Than Its H100(servethehome.com)
4 points by pbalcer 3y ago|0 comments
24.
by pbalcer 3y ago
On a tangentially related note, big companies often say that they perform pay benchmarking by contributing compensation data to third-parties to then determine the market rate for employees. After reading the article, it strikes me as a ver
25.
by pbalcer 3y ago
So? The fact that the most successful Arm server product is a proprietary one designed and used exclusively by one company literally proves OP point. It's much easier to support such deployment if you are its designer and sole user.
26.
by pbalcer 3y ago
There are enterprise database offerings that do something like that with RDMA. I'm almost certain CXL is being looked at for improvements.
27.
Add Full Support for the SYCL Programming Model (to LLVM)(discourse.llvm.org)
1 points by pbalcer 3y ago|0 comments
28.
by pbalcer 3y ago
+1. This is one of the most underappreciated things about the x86 CPU ecosystem. The documentation is usually solid, and all the Linux drivers are fully open-source and well maintained. Both AMD and Intel are almost always among the top con
29.
Numenta Has the Secret to AI Inference on CPUs Like the Intel Xeon Max(servethehome.com)
2 points by pbalcer 3y ago|0 comments
30.
by pbalcer 3y ago
no, that won't work. You'd have to clflush after every store. And even then, the cacheline might only ever get to the write pending queue (wpq) - and that you can't control.

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