oelang

9 ms·

1.
by oelang 6mo ago
VHDL mostly lost the ASIC consumer market and for some that's the only market that matters, but the hardware design ecosystem is much bigger than that. I wonder what AI will do to RTL/verification, the rigid nature of VHDL may be
2.
by oelang 6mo ago
(System)Verilog has delta cycles too you know, they call it an event queue, but it's basically the same. It's the direct variable updates that happen outside of this mechanism that cause all the issues. Imho it was a poor attempt
3.
by oelang 6mo ago
It's important to have deterministic simulations and semantics that you can reliably reason about. Both VHDL and SystemVerilog offer this to some extent, but in the case of (System)Verilog the order of value updates is not as strictly
4.
by oelang 6mo ago
VHDL still dominates in medical, military, avionics, space etc. and it's generally considered the safer RTL language, any industry that requires functional safety seems to prefer it. It's also the most used language for FPGA in Eu
5.
by oelang 9mo ago
And I wish you read the article, you're comments are completely off topic.
6.
by oelang 2y ago
Jim was involved in the early versions of Zen & M1, I believe he knows. Apples M series looks very impressive because typically, at launch, they are node ahead of the competition, so early access deals with TSMC is the secret weapon thi
7.
by oelang 2y ago
Microsoft recently announced that they run chatgpt 3.5 & 4 on mi300 on Azure and the price/performance is better. https://www.amd.com/en/newsroom/press-releases/2024-5-21-amd...
8.
by oelang 2y ago
AMD is already competitive on inference
9.
by oelang 3y ago
Any sensor that captures a ton of data that needs realtime processing to 'compress' the data before the data can be forwarded to data accumulator. Think MRI or CT scanners but industrially there are thousands of applications. If y
10.
by oelang 3y ago
The transformer engine is a fairly recent development (april this year I think) so I don't think they're very far behind.
11.
by oelang 3y ago
They have improved their software significantly in the last year, but there is a movement that's broader than AMD that wants to get rid of CUDA. The entire industry is motivated to break the nvidia monopoly. The cloud providers, variou
12.
by oelang 3y ago
If you're looking for fair comparisons don't ask nVidias marketing department, those guys are worse than Intel. What AMD did was a true comparison, while nvidia is applying their transformer engine which modifies & optimizes s
13.
by oelang 9y ago
> refers to scalability of the syntax And the flexibility of the type system and the advanced type inference.
14.
by oelang 9y ago
Well you're wrong, you can't run VS Code on the cloud.
15.
by oelang 9y ago
There are many examples: a pci-express bus or an application optimized ddr controller or a full tcp/ip stack or a caching/prefetch system or any advanced processor with feedback .... these kinds systems require precise control. It
16.
by oelang 9y ago
> Where did you get %20 percent number? I get the 20% number from a real world case, guys who converted a huge existing vhdl design into HLS with the help of several Xilinx FAEs, the application was ideal for HLS. > On the other hand,
17.
by oelang 9y ago
This is a very old (I think > 15 years ago) competition, the results say nothing about the situation today, both language have changed a lot. It was a PR stunt by the Synopsys guys who a that time wanted to kill VHDL. The VHDL guys had t
18.
by oelang 9y ago
Let me guess, you were downcasting everything to std_logic_vector? If you have to cast things all the time in VHDL you're not using it correctly. But please enjoy (System)Verilog with it's random often undefined coercion, implicit
19.
by oelang 9y ago
The verbosity of VHDL isn't 2x it's more like 20% bigger on average and since VHDL 2008 it's pretty much the same. VHDL can be wordy but it also reads a lot easier & it looks more structured. Verilog isn't C, it&#x27
20.
by oelang 9y ago
No they haven't and they are not even close. OpenCL is a bad language for synthesis. The strength of an FPGA is deeply-pipeline-able sequential algorithms. C-based languages just aren't good at expressing/controlling pipelini
21.
by oelang 9y ago
VHDL is an old version of ADA combined with a build-in discrete event simulator. The syntax, type system, general semantics are all copied from ADA. This is actually a good thing, Verilog (and even more SystemVerilog) is designed by people
22.
by oelang 9y ago
Be honest though, HLS works well for DSP-like applications, not for anything else. Not every digital design is image processing and if it works well you're still sacrificing ~20% of your LUTs.
23.
by oelang 10y ago
I'm surprised that you found it to be inconsistent. Care to give some examples?
24.
by oelang 10y ago
How could that dirt be worse than what we have/had on Trump? Does it even matter?
25.
by oelang 10y ago
We're 2017, VHDL 2008 was released 9 years ago, and this book is using VHDL 93.
26.
by oelang 10y ago
> Go is a language that is a bit tedious to write, no doubt about that, but it's very easy to read. I spend a lot of my time reading other people's code and I really appreciate that. Figuring out 1000 lines of code that could h
27.
by oelang 10y ago
> though I find the syntax aesthetically offensive Well that's indeed your opinion, whenever I write code in a language with old fashioned statements I die a little inside. I have a lot of experience with ADA too, at it's core
28.
by oelang 10y ago
It's funny that both java & c# seem to be picking up many scala features in their latest & future versions like traits, lambdas, tuples, pattern matching, case classes, closed hierarchies, declarative generics... Your language
29.
by oelang 10y ago
The way you describe your experience with Scala makes me think you only had a very superficial look at it. At it's core Scala is very simple & the syntax is very regular, far more than Go or Java and a lot less complex than C++. It
30.
by oelang 10y ago
http://www.scala-lang.org/old/node/8579

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