obl

6 ms·

1. 1.▲
   Leaving the Sea of Nodes in the V8 JIT(v8.dev)

   20 points by obl 4mo ago|2 comments
2. 2.▲
   by obl 2y ago

   It is not ridiculous at all. Those things have pretty precise definitions and type segregation absolutely does remove a bunch of soundness issues related to type confusion. You can think of it as the rather classic "Vec of struct + num
3. 3.▲
   The Elusive Frame Timing(medium.com)

   2 points by obl 2y ago|0 comments
4. 4.▲
   2024 EuroLLVM – How Slow Is MLIR [video](youtube.com)

   1 points by obl 2y ago|0 comments
5. 5.▲
   Maya as Editor: The game development approach of Santa Monica Studio [video](youtube.com)

   1 points by obl 2y ago|0 comments
6. 6.▲
   by obl 3y ago

   Weird that this treats uninitialized variables as unknown values. For example in ex3.c, the program int main(){ int x; if (x <= 42){ assert(x != 12345); } } is of course UB in C, even though under
7. 7.▲
   Parallel Query Systems: Demand-Driven Incremental Compilers [pdf](diva-portal.org)

   1 points by obl 3y ago|0 comments
8. 8.▲
   2023 LLVM Dev Meetingg – Mojo: A system programming language [video](youtube.com)

   2 points by obl 3y ago|0 comments
9. 9.▲
   eBPF: Unlocking the Kernel [Official Documentary] [video](youtube.com)

   1 points by obl 3y ago|0 comments
10. 10.▲
    LLVM: Scalar Evolution (SCEV)(npopov.com)

    1 points by obl 3y ago|0 comments
11. 11.▲
    Unreal Engine 5: Nanite deep dive [pdf](advances.realtimerendering.com)

    5 points by obl 3y ago|0 comments
12. 12.▲
    Chasing the Myth of Zero-Overhead Memory Safety(verdagon.dev)

    4 points by obl 3y ago|1 comments
13. 13.▲
    A CPU research kernel for cycle-by-cycle micro-architectural introspection(gamozolabs.github.io)

    5 points by obl 3y ago|0 comments
14. 14.▲
    by obl 3y ago

    This is memory safe if you never re-use a (generational index, address) pair. They seem to use 64 bit ones so this means that to overflow a single memory cell you would have to allocate and free it every cycle (!) at 4 ghz for about 150 yea
15. 15.▲
    From Stacks to Trees: A new aliasing model for Rust(ralfj.de)

    191 points by obl 3y ago|42 comments
16. 16.▲
    V8 Maglev: compiler design doc(docs.google.com)

    49 points by obl 3y ago|17 comments
17. 17.▲
    by obl 4y ago

    Actual clipping is expensive so indeed a "guard band" is used : inside the region allowed by the internal precision of the rasterizer, outside pixels are simply "ignored". See e.g. https://fgiesen.wordpress.co
18. 18.▲
    by obl 4y ago

    It would be interesting to see how you were testing for that, because at least on AMD it's fairly certain that a single thread can be shading multiple primitives. For example, from the ISA docs [1], pixel waves are preloaded with an SG
19. 19.▲
    by obl 4y ago

    In actual hardware shading is done 32 or 64 pixels at a time, not four. The problem above just got worse. While it's true that there are "wasted" execution in 2x2 quads for derivative computation, it's absolutely
20. 20.▲
    Ownership You Can Count on [pdf](inko-lang.org)

    2 points by obl 4y ago|0 comments
21. 21.▲
    A new runtime for Nim (2019)(nim-lang.org)

    2 points by obl 4y ago|0 comments
22. 22.▲
    Semantic Subtyping in Luau(blog.roblox.com)

    2 points by obl 4y ago|0 comments
23. 23.▲
    by obl 4y ago

    If you didn't already, I'd recommend compiling llvm/clang in debug or release+assert mode when working on it. The codebase is quite heavy in debug-only assertions even for relatively trivial things (like missing implementatio
24. 24.▲
    SSA Translation is an Abstract Interpretation [pdf](binsec.github.io)

    1 points by obl 4y ago|0 comments
25. 25.▲
    A Decade Verifying LLVM, or How to Retrofit Soundness in Industrial Software(youtube.com)

    2 points by obl 4y ago|0 comments
26. 26.▲
    Const Syntax in Rust(blog.yoshuawuyts.com)

    1 points by obl 4y ago|0 comments
27. 27.▲
    Carbon’s most exciting feature is its calling convention(foonathan.net)

    243 points by obl 4y ago|217 comments
28. 28.▲
    by obl 4y ago

    Wait, I'm pretty sure operand collection logic & banking is there to keep the number of ports on the SRAM low, so basically you're arbitrating and buffering requests coming from high register count instructions (say 3 input fm
29. 29.▲
    Make Your Own Chips for Free(efabless.com)

    127 points by obl 4y ago|92 comments
30. 30.▲
    The B3 JIT Compiler (2016)(webkit.org)

    1 points by obl 5y ago|0 comments