jpieper

5 ms·

1.
by jpieper 3mo ago
Isn't it obvious? The creator gets paid much more, in whatever currency they care about: - ad revenue - youtube algorithm placement - sponsored content - street cred With an article, if you're lucky google will base their AI over
2.
by jpieper 4y ago
Beginner pytorch user here... it looks like it is using only one CPU on my machine. Is it feasible to use more than one? If so, what options/env vars/code change are necessary?
3.
by jpieper 4y ago
I'm curious what other OSS firmware is using the G4 series?
4.
by jpieper 4y ago
No, but out of pins connected to timers with the appropriate capabilities.
5.
by jpieper 4y ago
Yeah, I have (maybe slightly fond?) memories of using Forth to develop a tape drive reader and writer for an undergraduate lab project. It is wonderful for some things, although in this case, where the problem was literally which addresses
6.
by jpieper 4y ago
Yep, there is probably one clock domain for all the ADCs, although there are two different prescalers (one for ADC1/2 and another for 3/4/5). I could see one of the writes getting lost. In this case though, the ADC enable is
7.
by jpieper 4y ago
Here "allocation" is all fixed size things pulled from a fixed size buffer at startup. Technically malloc is compiled in the firmware, but it isn't used for anything but some C++ runtime initialization confirmed with debugge
8.
by jpieper 4y ago
That is possible, although here the consecutive writes were to different ADC peripherals. The ADC peripherals do share some common configuration and triggering, but I believe are otherwise largely independent.
9.
by jpieper 4y ago
In this case, the firmware did wait for the ADRDY flag. It just waited for all 5 to be set, then moved on to enable all 5 ADCs simultaneously. The easy fix was to just do those serially instead.
10.
by jpieper 4y ago
Actually, if you look at the firmware at the time, the proper procedure was followed as far as I can tell. All of the necessary bits were set and checked with the appropriate delays where required. https://github.com/mjbots
11.
by jpieper 4y ago
For what it is worth, the G0/4 family is relatively new. I'm pretty sure it has unique ADC IP too, since the published errata (which I'm very familiar with) are different from any other ST chip I know of. The clock should of
12.
by jpieper 4y ago
Order far in advance....? These particular chips arrived more than a year ago. But yes, the shortage is hitting hard here too. The last tray I received was one year ago, after which all orders have been unfulfilled.
13.
by jpieper 4y ago
Surprisingly, it is almost certainly genuine. These particular chips likely came from a batch delivered in April of 2021 from Mouser, who isn't known for their shoddy sourcing practices.
14.
Debugging bare-metal STM32 from the seventh level of hell(jpieper.com)
166 points by jpieper 4y ago|68 comments