jamesissac

5 ms·

1. 1.▲
   by jamesissac 7y ago

   Being able to observe all inputs sources at the same time requires extra hardware(more utilisation of the FPGA resources), considering only one input is connected to the display at a time. So it's probable that the check is sequential.
2. 2.▲
   by jamesissac 8y ago

   Do checkout Xilinx's Zynq series or Altera's Cyclone series, I think that may be what you're inferring ?
3. 3.▲
   by jamesissac 8y ago

   Maybe the downside is that Bob will observe that others express displeasure at his behavior, having let down their expectations(maybe unreasonable) of him. Now Bob isn't callous by nature so this will weigh upon his conscience.
4. 4.▲
   by jamesissac 8y ago

   I can identify with a couple of the points and I can be quite miserable at times. I'm working on addressing it.