j_seigh

8 ms·

1.
by j_seigh 15d ago
Not enough caffeine. And yeah, it would have been phosphine since it was phosphorous that was the dopant.
2.
by j_seigh 15d ago
Some places would mix it with nitric acid so the yellow stain would tell you that you had been exposed. Other fun chemicals used in fabs were Silane (CSi4), methane w/ silicon instead of hydrogen, used to form a silicon dioxide layer f
3.
by j_seigh 20d ago
I'd be more concerned with instruction reordering by the compiler. So even if the hardware guarantees some ordering, you will still need those memory fences.
4.
by j_seigh 2mo ago
Sort of. Basically you have a situation where one thread needs to see another thread's memory accesses in sequential consistent order. If you can determine the other thread has synchronized its memory accesses at some point, then all
5.
by j_seigh 2mo ago
For hazard pointers it was proposed here https://groups.google.com/g/comp.programming.threads/c/XU6Bt... I did a POC afterwards. For linux it was a bit PITA since /proc text had to be parsed to track con
6.
by j_seigh 4mo ago
Lighting rods also work by dissipating the local electric potential and reducing the likelihood of a lightning strike. That's why they are pointed, or fractal in the newer ones. From https://en.wikipedia.org/wiki/
7.
by j_seigh 5mo ago
Couldn't traceroute run the entire TTL range in parallel, assuming the destination host was reachable and replies are disambiguable? I always hated waiting for traceroutes with lots of non responding routers.
8.
by j_seigh 6mo ago
My impression was LL/SC had forward progress issues due to the difficulties of preventing false sharing of the locked memory reservation region. Updates into that region would keep invalidating the lock. I had a version of atomic* ref
9.
by j_seigh 6mo ago
It seems almost nobody can spell lose correctly anymore. I assume it's deliberate.
10.
by j_seigh 9mo ago
The comments about HFT needing tightly synchronized clocks got me thinking. Back in the day, way back in the 80's, IBM replaced the VM with VMXA. VM could trap and emulate all the important instructions since they were privileged inst
11.
by j_seigh 9mo ago
Ok,so people use NTP to "synchronize" their clocks and then write applications that assume the clocks are in exact sync and can use timestamps for synchronization, even though NTP can see the clocks aren't always in sync. Do
12.
by j_seigh 9mo ago
I did a lock-free MPMC ring buffer with 1 128 bit CAS and 1 64 bit CAS for enqueue and 1 64 bit CAS for dequeue. The payload is an unrestricted uintptr_t (64 bit) value so no way to avoid the 128 bit CAS in the enqueue.
13.
The ABA Problem Cost Us $50K: A Cautionary Tale(lucisqr.substack.com)
3 points by j_seigh 10mo ago|1 comments
14.
by j_seigh 10mo ago
Paywalled, but if you are familiar with the ABA problem in lock-free programming you can pretty much figure things out.
15.
by j_seigh 11mo ago
Coherent cache is transparent to the memory model. So if someone trying to explain memory model and ordering mentioned cache as affecting the memory model, it was pretty much a sign they didn't fully understand what they were talking
16.
by j_seigh 11mo ago
How is this different than something like https://www.espertech.com/
17.
by j_seigh 1y ago
I'm assuming they're using an unbounded MPMC queue. With GC you can use a lock-free queue, otherwise you have to use mutexes, or reference counting which is nearly as bad.
18.
by j_seigh 1y ago
I did do an actual lock-free MPMC ring buffer implementation as an exercise. I used that to make blocking bounded queues using various synchronization mechanisms, mutex/condvars and eventcounts among others. The eventcount version runs
19.
by j_seigh 1y ago
Only using way more bits. The original IBM lock-free stack algorithm assumed 32 bits was safe because it would take 100 years for a 32 bit counter to wrap at the time. Now it's less than 1 second. There's some Bugblatter Beast l
20.
by j_seigh 1y ago
I did find some links to some of my old posts on restartable sequences for user space rcu. Looked into using unix signal handling but it was pretty problematic to put it mildly. Definitely something you had to implement in the kernel. ht
21.
by j_seigh 1y ago
It's worse than you think. I've closed PayPal accounts and opened new ones with a different email address and PayPal updates the merchants who've been spamming me with the new email address. There's no legitimate techn
22.
by j_seigh 1y ago
I don't think it has to be. Conceptually it's just a couple of queues. There's a software equivalent of the Peter Principle where software or an API becomes increasingly complex to the point where no one understands it. The
23.
by j_seigh 1y ago
https://groups.google.com/g/comp.programming.threads/c/XU6Bt... https://groups.google.com/g/linux.kernel/c/gk6AUkXR9As/m/-1W... Yes, I am aware of the asymmetric memo
24.
by j_seigh 1y ago
Bakery locks are good for spin locks. They're more cache friendly. Plus you can do reader/writer spin locks. They're going to be strictly FIFO though. I guess you could tack on a futex wait for the spin wait in user space
25.
by j_seigh 1y ago
Here's an interesting scheme. Some credit/debit card merchant accounts can arrange to get updated card info if your card expires and/or gets replaced. So if the merchant is a bad actor and doesn't charge your card dire
26.
by j_seigh 1y ago
One of the few places I get a citation. It's where the idea of asymmetric memory barriers came from. RCU is used as the quiescent states are context switches which gives you a memory barrier on the thread doing the context switch. Th
27.
by j_seigh 1y ago
ChromeOS flex. It will run on hardware that even Linux complains about. I've even installed it on a Chromebook that stopped getting updates. Though, you have to replace the firmware, which entails some risk of bricking, so you can d
28.
by j_seigh 1y ago
Thread local vars would be used with lazy initialization. Clean up might be a little tricky depending on what implementation of thread local you use. Thread local support is not as great as it should be.
29.
by j_seigh 1y ago
You just need to keep track of each thread's quiescent states however they are implemented.
30.
Wait-Free Hazard Pointers Using Std Atomics(threadnought.wordpress.com)
1 points by j_seigh 1y ago|1 comments

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