gluggymug

10 ms·

1.
by gluggymug 8y ago
I believe Tcl scripts can help automate your FSBL and BSP changes. Pretty much everything you do in the GUI translates to Tcl commands.
2.
by gluggymug 9y ago
There is a distinction between hardware emulators and FPGAs. Though hardware emulators such as Palladiums may use FPGAs inside them they don't work the same way in terms of validation. The two tools are very different to use. See myth
3.
by gluggymug 9y ago
At the SoC level, I don't think so. The reasons are numerous. I already gave a few. I will give another. Once you have to integrate hard IP from other parties, you cannot synthesise it to FPGA. Which means you won't be able to run
4.
by gluggymug 9y ago
"If you're Intel or AMD making a processor, I bet FPGA versions of things are not terribly relevant because it doesn't capture a whole host of physical effects at the bleeding edge." Exactly. When you verify a design via
5.
by gluggymug 9y ago
I don't agree. If it's non trivial, I don't have the more advanced verification tools such as UVM if I prototype via FPGA. The ability to perform constrained randomised verification is only workable via UVM or something like
6.
by gluggymug 9y ago
As a veteran from the chip industry, I should warn you that all these suggestions about FPGAs for prototyping are not really done that much in the ASIC industry. The skills to do front end work are similar but an ASIC design flow generally
7.
by gluggymug 9y ago
I say "terribly-designed curriculum". Maybe engineers need to be introduced to the synthesis tools at the same time as the simulator tools. Simulating RTL is only an approximation of reality. So emphasizing RTL simulation is bad.
8.
by gluggymug 9y ago
If you are not an old fart like myself, you probably haven't used an actual Unix system but back in the days before the popularity of Linux, you'd see a lot of Solaris. You stuck to your guns and didn't just lie about Unix ex
9.
by gluggymug 9y ago
It's the experimental part of the high level language that is the problem. I agree you shouldn't teach it to students. It just leads them down a divergent path away from what is done in industry. It isn't addressing the nee
10.
by gluggymug 9y ago
"One thing that bit me when I was a complete n00b: assigning registers from within more than a single always block. On my simulator (at the time) it worked perfectly but the synthesis tool silently ignored one of the blocks." It&#
11.
by gluggymug 9y ago
The problem is that reset logic requires a bit of design rather than hard fast rules. Designs are getting larger these days with a lot of 3rd party IP that you can't assume use a particular reset method. Tips #2 and #5 in this article,
12.
by gluggymug 9y ago
I agree about the parallelism but you have to understand the design methodology. Your example is somewhat pointless. The code is written to create the HW not the other way around. I can't feed it just any crap. You want parallelism you
13.
by gluggymug 9y ago
As a long time HW FPGA guy, I think you might want to take a look at the C projects again. I don't know whether Go has any advantages but the concept of a higher level language for development is being used by the major FPGA companies.
14.
by gluggymug 9y ago
>- jump to previous commands. >You just ran a command that printed a few pages, you want to scan from the first line. I think tmux might get you there. You bind a key to enter copy-mode and backward search for your parti
15.
by gluggymug 9y ago
>Lack of electronics knowledge is what prevents most software developers from being productive in Verilog. A "better" language won't help. I am working in the FPGA industry. I definitely agree with you. But possibly I am a
16.
by gluggymug 9y ago
How long have you had your current job? Median tenure is falling I believe. And employees in their mid-twenties and thirties have way lower tenure than those in their fifties. I think it's about 3 years as opposed to 10 years. Job-hunt
17.
by gluggymug 9y ago
A few years ago there was an exposé on 457 abuse in the IT industry on national tv.( http://www.abc.net.au/7.30/content/2013/s3786315.htm ) Hence the "TCS" jab from empressplay. A lot of IT contracts
18.
by gluggymug 9y ago
The OA is talking a bit more specifically than just getting kids to play IMO. His title is Head of Innovation. Innovation is corporate-speak for actual company processes where they change things up like their business model, or their target
19.
by gluggymug 9y ago
I think CASE 3 is going to be much faster due to the high performance AXI ports that Zynq's have.
20.
by gluggymug 9y ago
Cool project. As someone from the FPGA industry, bigger projects just use your CASE 3 on a board to start prototyping. A Zedboard or similar. Cheaper version could be the Zybo. It's like $500 vs $200. When you get to production stage,
21.
by gluggymug 10y ago
In Russia, that's not considered as an insult.
22.
by gluggymug 10y ago
It's all about bad management. But it's about how they make plans and deadlines in the first place. If they don't spare a thought for what future problems can come up and make allowances and contingencies for these risks then
23.
by gluggymug 10y ago
The comments on this thread have been more interesting than the article. I think the common theme is a push to innovate and take the next step in computer systems. If we scan this thread we could come up with a list of issues/problems
24.
by gluggymug 10y ago
There's only one example there. http://www.aviduratas.de/lisp/lispmfpga/code.html
25.
by gluggymug 10y ago
No way to specify different clocks or resets from what I can see. That's a massive limitation to your designs.
26.
by gluggymug 10y ago
You've pretty much hit the nail on the head. What people outside of the EDA field fail to understand is they are coding at a much higher level. RTL does not model all the aspects of the logic. You have different signal delays due to l
27.
by gluggymug 10y ago
Things don't just work automatically. Some idiot can throw a design in that doesn't just synthesize. After synthesis, your RTL becomes a gate level representation. You then place your logic i.e. Your memory logic near your memorie
28.
by gluggymug 10y ago
"We've already seen this happening on the HDL side of things; open-source, research-driven efforts like Clash and Chisel are orders of magnitude better than the crap that industry has been using for years (VHDL and (System) Verilo
29.
by gluggymug 10y ago
Not quite because you have a few more steps in the process after the design phase. For instance, you need to perform testing on the fabricated parts to determine if there are physical defects. That means creating the tests then paying for t
30.
by gluggymug 10y ago
From http://infohub.ifoam.bio/sites/default/files/page/files/misc... Referring to pesticides: "Organic standards-setting bodies are responsive to new data on toxicity of natural substances and

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