eigenform

6 ms·

1.
by eigenform 9d ago
Lovely work, thanks for sharing!
2.
by eigenform 13d ago
Fascinating, thank you. It seems strange that the C1-Pro/C1-Ultra TRM mention that ID_AA64PFR1_EL1[11:8] should still be non-zero even when BROADCASTMTE is low. edit: Oh, I guess Linux does emulate the feature registers, doh. Since tha
3.
by eigenform 14d ago
> It's possible to enable reserving the tag memory for MTE via `fastboot oem mte on`, boot a non-stock kernel ignoring arm64.nomte and use MTE. What I'd like to know is, is it not sufficient to just check the feature bits in ID
4.
by eigenform 23d ago
What you want is a proof that microarchitectural timing differences (ie. the difference between a cache hit and cache miss) cannot possibly turn into architecturally-visible timing differences. If a program cannot reliably distinguish bet
5.
by eigenform 23d ago
It's good to be skeptical about how we implement the idea of a "root of trust" in these machines, but matter-of-factly characterizing ME and PSP as "backdoor" is misleading and not useful.
6.
by eigenform 29d ago
So did anyone actually figure out what the issue was?
7.
by eigenform 2mo ago
Sorry, when talking about things from the hardware's point of view, I'm in the habit of using the word "programmer" to also mean "the compiler"!
8.
by eigenform 2mo ago
Yes, I'm pointing out the fact that the programmer is expected to manage the ALAT, and that these machines do not automatically recover from cases where your advanced loads are incorrect. That process is expected to be part of the inst
9.
by eigenform 2mo ago
The difference is that this is not the programmer's responsibility in modern machines: instead we bake-in some hardware that watches the online state of the machine and then actively decides on what to do. If you're trying to crea
10.
by eigenform 3mo ago
Additionally, if you look at the changelogs for old ABL, it seems like this policy decision (only supporting for PRO SKUs) has always been implemented in firmware: https://github.com/amd/firmware_binaries/blob&#x
11.
by eigenform 4mo ago
Well, the FDIV bug is simpler. AFAICT this whole thing is tied up in the relationship between DVFS, silicon aging, and being able to have guarantees about clock reliability. That seems hard to reason about when you give BIOS vendors and use
12.
by eigenform 5mo ago
afaict part of the messaging behind this quake is about the worry that big Sanriku earthquakes like this might make it easier for the northeast part of the trench to unlock (closer to Aomori and Hokkaido, where the Japan Trench starts turni
13.
by eigenform 5mo ago
No reason that the rate of subduction has to be the same everywhere. Some of the plate boundaries might be moving into each other in different directions too, the coupling between plates is not necessarily the same everywhere. Anyway, in th
14.
by eigenform 6mo ago
The idea here is about maintaining a "path history"! When looking up a register that tracks the "local" history of outcomes for a particular branch, you want to have a hash function that captures enough context to distin
15.
The most precise mechanical indicators ever made – The Mikrokator [video](youtube.com)
3 points by eigenform 8mo ago|0 comments
16.
by eigenform 8mo ago
please stop posting worthless drivel from your language model, thank you. it really cheapens the meaning of all these fancy words.
17.
by eigenform 8mo ago
ie. marketed as "dense" instead of "efficient"
18.
by eigenform 11mo ago
Probably because it's very likely that both AMD and Intel have had engineers working on this sort of thing for a long time, and they're now deciding to collectively hash out whatever the solution is going to be for both of them.
19.
by eigenform 11mo ago
I'm not arguing MPX was a good solution, just that it's silly to assume folks designing x86 machines have been totally ignoring developments in that space for the past ten years.
20.
by eigenform 11mo ago
fwiw "knee-jerk reaction to Apple MIE" is not exactly the right characterization of this. MPX existed and faded away, and it's not very surprising that x86-world would wait for someone else to try shipping hardware support fo
21.
by eigenform 11mo ago
I wonder if this is in response to FineIBT trying to figure out what to use as an undefined opcode? Apparently 0xd6 is being reserved as undefined going forward: https://lore.kernel.org/lkml/20250814111732.GW4067720@noi
22.
by eigenform 1y ago
Yeah totally. It's really easy to forget about the fact that x86 is abstracting a lot of stack operations away from you (and obviously that's part of why it's a useful abstraction!).
23.
by eigenform 1y ago
> x86 CALL/RET I wonder if anyone has actually measured what the code size savings from this look like for typical programs, that would be an interesting read. RISC trope is to expose a "link register" and expect the progr
24.
by eigenform 1y ago
didn't realize that since the last time i looked at these docs, seems like they've added lots of nice block diagrams for all the different parts of the machine. neat!
25.
Arm MTE and Speculative Oracles(reflexive.space)
3 points by eigenform 1y ago|0 comments
26.
by eigenform 1y ago
Since everyone is upset about the lack of technical details in the article, I'll try: The takeaway from that paper (imo, afaict) is that guest userspace can influence indirect predictor entries in KVM host userspace. I don't reall
27.
by eigenform 1y ago
Yeah, they wrote a paper about the ALUs too, see: https://ctho.org/toread/forclass/18-722/logicfamilies/Delega... > There are two distinct 32-bit FCLK execution data paths staggered by one clock to im
28.
by eigenform 1y ago
Not even true: Arm, Intel, AMD, and most other hardware vendors (who are actively making an effort to support Linux on their parts) actually publish useful[^1] documentation. edit: Also, not knocking the Qualcomm folks working on Linux here
29.
by eigenform 1y ago
Not surprising considering I haven't seen a programming manual or actual datasheet for these things in the first place. Usually helps if you tell the community how to interact with your hardware ..
30.
by eigenform 1y ago
> preventing instructions from issuing seems like too hard of a requirement If this were the case, you could perform SYSCALL in the shadow of a mispredicted branch, and then try to use it to leak data from privileged code. When the machi

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