dougall

9 ms·

1.
by dougall 8mo ago
Hi, author here. My version definitely shouldn't be faster unless something very weird is going on with the runtime (though I think with the benefit of hindsight some further optimisation of it is possible). I have never seen a good us
2.
by dougall 2y ago
It's fun :)
3.
by dougall 2y ago
Yeah, exactly this. To try to make it more "concrete", compilers tend to end up processing an absurd mess of code, that does things that superficially look silly, due to extensive inlining. The code above is entirely plausible for
4.
by dougall 2y ago
Author here - I believe this 2020 post resurfaced as known-bits optimisation was recently added to PyPy (Python implementation using a JIT compiler), which this thread discusses: https://mastodon.social/@cfbolz/11255767
5.
by dougall 3y ago
Awesome! I'm always happy to hear people are interested in SVE :) (And yeah, creating technical documentation that a large company should have created themselves has somehow become a hobby of mine.)
6.
by dougall 3y ago
Heh, I'd have called it the Arm SIMD Instruction List, but Arm have been aggressively enforcing the Arm trademark [1], so I settled for A64 (the official name for the instruction set [2]). [1] https://www.theregister.com&#x2
7.
by dougall 3y ago
I hope it's useful, though I think most people care about the "Advanced SIMD" (Neon) instructions, which I'd also like to do. I started with SVE because I wasn't already familiar with it, so it was a more interestin
8.
by dougall 3y ago
It is a trade off, but a lot of processors have free offsets from loads, so pointer chasing is almost always free. On ARM, "ldr x0, [x1]" just becomes "ldur x0, [x1, #-1]" - same size, same performance (at least on the A
9.
by dougall 3y ago
The tag bit can be inverted. V8 uses 1 for pointers, 0 for integers - you're usually loading from constant offsets from pointers anyway, so that mostly folds away nicely. Then: x + y is translated to CPU instructions x + y x * y is tra
10.
by dougall 3y ago
Yeah... I don't know if you saw Rodrigo Branco's damning "The Microarchitectures That I Saw And The Ones That I Hope To One Day See": https://www.youtube.com/watch?v=WlcQrx7VK00 https://hardwe
11.
by dougall 3y ago
Browsers use multiple processes for security and reliability, not as an alternative to multi-threading. They extensively use multi-threading for performance (as does a lot of other modern software).
12.
by dougall 3y ago
Yeah – ARM specifically added EOR3 and BCAX instructions to accelerate SHA-3 hashes, both of which can be handled by VPTERNLOGD.
13.
by dougall 3y ago
Is there a reason you call out Discord and not GitHub?
14.
by dougall 3y ago
Good point, it's likely that a high-power in-order chip could go faster. Do you know of any examples of high-power in-order cores I could compare to?
15.
by dougall 3y ago
Alas, security generally isn't so important. How many times have you been hacked by a side-channel exploit? (Or people you know? Or any publicly documented case?) Are you going to use a computer that runs at 1/10th the speed to mi
16.
by dougall 3y ago
Nice! Sorry if this comment is overly pedantic, I just enjoy having an excuse to talk about assembly. It's worth noting that 0x80000000 would pass this "is zero" check. (I think this is probably a legal compiler optimisation
17.
by dougall 3y ago
Though it'd be preferable to do: cmp wzr, w19 // set the carry flag if w19 is zero adc w8, w19, w19 // w8 = w19 + w19 + carry
18.
by dougall 3y ago
Some: https://news.ycombinator.com/item?id=35301630
19.
by dougall 3y ago
Really? Is there case law to this effect? These things happen, and have value, but I wouldn't have considered them as "given as a quid pro quo" or "mutual promises".
20.
How I made Tracy 30× faster(wolf.nereid.pl)
3 points by dougall 3y ago|0 comments
21.
by dougall 3y ago
It's a huge issue, but multi-threading only helps with latency, not energy.
22.
by dougall 3y ago
Then do that. It's not a video codec. The problem is computation power is increasing much more slowly than bandwidth, and is likely to continue to. 8K PNGs (by my napkin calculations) already take around 1 second of CPU time to decode.
23.
by dougall 3y ago
Thanks! It's a tiny contribution compared to Alyssa and Lina's development and reverse engineering work, but it's been very educational and rewarding work so far :)
24.
by dougall 3y ago
My personal answer: It's good hardware. I like good hardware, so I'm pro-competition. Doing the work makes the hardware documented, for anyone to understand (mainly developers, but also Apple's competitors). Having more devel
25.
by dougall 4y ago
Yeah, looks like Intel desktops are currently ~10% ahead of Mac laptops in single-threaded performance: https://browser.geekbench.com/processors/intel-core-i9-13900... https://browser.geekbench.com/macs
26.
by dougall 4y ago
Feature support: https://github.com/AsahiLinux/docs/wiki/Feature-Support Asahi is still in Alpha. Expect things to be a bit rough.
27.
by dougall 4y ago
That toot is about upstream Linux 6.2, not Asahi Linux. If you run Asahi Linux (as in the blog post) you get decent (but not complete) legwork-free hardware support. Detailed breakdown here: https://github.com/AsahiLinux&#x2
28.
by dougall 4y ago
Every time there's an indirect branch (including a return) there's a chance that they will be inspected. The "unused flags" optimisation does remove most of them, in a way that gets it right 100% of the time (excluding s
29.
by dougall 4y ago
I've only messed around in user-space, so I'm not sure how it's enabled. But if I were to guess, it might be bit 4 ("Enable APFLG") of ACTLR_EL1 ("(ARM standard-not-standard)"): https://github.c
30.
by dougall 4y ago
They might know of some, but I'm of the opinion that it's worth it to support the specification. It only takes one previously undiscovered application to rely on that specified behaviour, and then you need to fix it. If it were so

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