davidlt

6 ms·

1.
by davidlt 1mo ago
It's the same pre-training, they are just adding more (+ better) SFT, RL, etc. (post-training). Model internal knowledge cut-off is still the same. It seems we are doing pre-training every 6 months, and post-training every 4-8 weeks no
2.
by davidlt 1mo ago
I just wanted to emphasize this. Harness is a big part of how things perform thus usually it's harness + model co-design that's important.
3.
AMD Publishes Open-Source Driver for GPU Virtualization, Radeon "In the Roadmap"(phoronix.com)
196 points by davidlt 1y ago|61 comments
4.
by davidlt 2y ago
This isn't a problem. See article [EN][0]. Simply put we are significantly below the cap. If somehow we would manage to hit the cap it definitely should be an alarm for investigation. I feel more folks are unhappy because EU was divide
5.
by davidlt 2y ago
I am really surprised with RNDA3 support. I have never seen so many issue with iGPU (APU). It started with VP9 decoder issue (e.g. just playing videos on YouTube was enough to trigger it), but that got fixed after a very long time (required
6.
by davidlt 3y ago
+1 on your initial comment. Exactly how I feel about the current situation. MilkV Oasis with SG2380 would be the end-game for majority of developers, but they are definitely loosing money if they keep starting price at 120 USD. They don&#x2
7.
by davidlt 3y ago
To my understanding SiFive continues to offer their selection of core IP. Anyways, I would assume any existing contract would have to be fulfilled for various legal reasons. SG2042 itself is T-HEAD C920 design which is a mess, and might not
8.
by davidlt 4y ago
Upstreasming status: https://rvspace.org/en/new-page/JH7110_Upstream_Plan StarFive Tech. have been upstreaming on kernel, OpenSBI and U-Boot from several weeks now. Of course this is still weeks/months away (
9.
by davidlt 5y ago
It could be that decision to not support AVX512 was made very late in product development and thus early batches didn't have chicken bit disabled or/and fused it off. There might be gazillions of reason why this was done.
10.
by davidlt 5y ago
Zba, Zbb, Zbc, Zbs (BitManip) have been approved by "Architecture Review" thus I assume they close to being ratified. Probably one of the first new extensions to be available for RISC-V. Because it's not ratified the BitMani
11.
by davidlt 5y ago
There are Profiles specs and Platforms specs, that will be regularly updated. This means software has a fixed target on which it can depend.
12.
by davidlt 5y ago
I am running RX 570 with PCIe + 6-pin connector for the power. These works out-of-the-box due to open source drivers. Older Nvidia cards work too, but you would need to go with older cards as you need Nouveau driver. I believe someone recen
13.
by davidlt 6y ago
For the price point they are going it's plenty enough. That's also enough to boot Linux distributions in headless mode.
14.
by davidlt 6y ago
IIRC Allwinner has already sent some patches related to RISC-V to kernel and also suggestions to SBI specification. So far the beginning is good. Remember that they are using IP from Alibaba. Alibaba might as well work on upstreaming, etc.
15.
by davidlt 6y ago
06:34PM EDT - Q: plans to support RVV 1.0? A: 0.7.1 for now - when we designed, it was still at that level. We are following and working on that yes. From https://www.anandtech.com/show/15991/hot-chips-2020-live-bl
16.
Intel Releases Thunderbolt 3 Protocol (royalty-free) [base for USB 4](newsroom.intel.com)
3 points by davidlt 8y ago|0 comments
17.
by davidlt 8y ago
Yesterday I decided to configure unbound on fresh Fedora 28 Beta install and configure it to use DNS-over-TLS to Cloudflare and Quad9. unbound runs as local recursive resolver. Within a laptop it's decrypted, but all outside communicat
18.
by davidlt 9y ago
We are working on Fedora RISC-V.
19.
FOSDEM 2018: Major SiFive Reveal in less than 12 hours (RISC-V)
1 points by davidlt 9y ago|0 comments
20.
by davidlt 9y ago
IIUC, a limited number of people from kernel community knew about this and NDAs didn't exactly allow all the parties work together. The first solutions/mitigations exist (might not be nice), but now embargo is lifter and the commu
21.
by davidlt 9y ago
On ARM (A64, A32, T32) we get CSDB barrier, but it's a hint instruction instead of going via MSR registers. From whitepaper CSDB is 1101_0101_0000_0011_0010_0010_100_11111 Here some snippets from ARM manuals: HINT instruction: 1101 010
22.
by davidlt 9y ago
Cortex A53 and A55 (in-order designs) are not vulnerable to any variant. ARM Ltd. provide details for all of their designs (it's a bit like Swiss cheese, each core is vulnerable to different variants). Thus low/mid-tiers and half
23.
by davidlt 9y ago
Stable ABI. We have done ~Fedora 25 in late 2016 - https://fedoraproject.org/wiki/Architectures/RISC-V and you can even boot that in your browser - https://bellard.org/jslinux/ ABIs have cha
24.
Q&A on ARM Mali-G72 [video](youtube.com)
1 points by davidlt 9y ago|0 comments
25.
Q&A on ARM Cortex-A75, ARM Cortex-A55, ARM DynamIQ [video](youtube.com)
1 points by davidlt 9y ago|0 comments