daemonwrangler

7 ms·

1. 1.▲
   by daemonwrangler 11y ago

   Sort of. The physical register file has more registers than what's specified in the ISA in order to support out-of-order execution. Hardware maps the small number of ISA registers to the larger number of physical registers. All sorts o
2. 2.▲
   by daemonwrangler 11y ago

   Also simpler to decode. If you look at how much chip area goes to the frontend decoder in an x86 chip, that's a significant difference.
3. 3.▲
   by daemonwrangler 11y ago

   Can you use memory locations as operands in most instructions in the RISC ISAs these days? I always liked that RISC tended to have explicit Load and Store instructions to bring memory values into registers vs. being able to specify a regist
4. 4.▲
   by daemonwrangler 11y ago

   Because it's easy to calculate? Too bad it's also utterly meaningless.
5. 5.▲
   by daemonwrangler 11y ago

   Something else to keep in mind is that you can get significant power savings when you lower the clock rate. So if you measure total power consumed to run a calculation, it may actually be more efficient to run on a fast CPU, finish quickly,