clamchowder

7 ms·

1.
by clamchowder 1y ago
(author here) they try for all instructions, just that it's a prediction w/replay because inevitably some instructions like memory loads are variable latency. It's not like Nvidia where fixed latency instructions are statical
2.
by clamchowder 1y ago
It does clock ramp from 800 MHz idle to 3.2 GHz under load, with 900, 1000, 1100, 1300, 1500, 1800, 2200, and 2700 MHz steps in between until it hits 3.2 GHz after 71.6 ms. Article was getting long enough so I just left it at, it reaches 3.
3.
by clamchowder 2y ago
It was a joke about blurriness. To extend the joke, be glad it doesn't flicker and shimmer. But yes, platforms usually apply compression in terrible ways, and it's especially noticeable coming from text and straight line stuff lik
4.
by clamchowder 2y ago
Yea Wordpress was a terrible platform and Substack is also a terrible platform. I don't know why every platform wants to take a simple uploaded PNG and apply TAA to it. And don't get me started on how Substack has no native table
5.
by clamchowder 2y ago
(author here) When I checked the 7600 XT was much more expensive. Right now it's still $360 on eBay, vs the B580's $250 MSRP, though yeah I guess it's hard to find the B580 in stock
6.
by clamchowder 2y ago
Oh that should be fun. Would have to fit it around work though
7.
by clamchowder 2y ago
"don't run any faster than a sequence of simpler instructions" This is false. You can find examples of both x86-64 and aarch64 CPUs that handle indexed addressing with no extra latency penalty. For example AMD's Athlon t
8.
by clamchowder 2y ago
No, that's not a second level BTB in that regular direct branches don't seem to use it. It's only for predicting indirect branches.
9.
by clamchowder 2y ago
(author here) Just a 32 entry BTB is technically a possibility from microbenchmark results, but the EIC7700X datasheet straight up says: "a branch prediction unit that is composed of a 32-entry Branch Target Buffer (BTB), a 9.1 KiB-ent
10.
by clamchowder 2y ago
(author here) I compared it to the A75 on the Snapdragon 670, not the 845. I chose that comparison because I have a Pixel 3a (my previous daily driver cell phone), and that's the only A75 core I had access to.
11.
by clamchowder 2y ago
(author here) by free time and curiosity I mean, I have a day job so I'm able to do this as my hobby
12.
by clamchowder 2y ago
Note - I saw the article through from start to finish. For power measurements I modified my memory bandwidth test to read AMD's core energy status MSR, and modified the instruction bandwidth testing part to create a loop within the tes
13.
by clamchowder 2y ago
Yes, I tested on CCD1 (the non-vcache CCD) on both BIOS versions.
14.
by clamchowder 2y ago
Seems like no one ever reads the byline anymore
15.
by clamchowder 2y ago
1. Yeah I agree, both X Elite and many Intel/AMD chips clock well past their efficiency sweet spot at stock. There is a cost to extra pipeline stages, but no one is designing anything like Tejas/Jayhawk, or even earlier P4 variant
16.
by clamchowder 2y ago
1. Performance. Also Arm implemented instruction cache coherency too. Predecode/uop cache are both means to the same end, mitigating decode power. AMD and Intel have used both (though not on the same core). Arm has used both, including
17.
by clamchowder 2y ago
Some notes: 1. Consider M1's 8-wide decoder hit the 5+ GHz clock speeds that Intel Golden Cove's decoder can. More complex logic with more delays is harder to clock up. Of course M1 may be held back by another critical path, but i
18.
by clamchowder 2y ago
Oh I don't mind the discussion here at all, I'm just occasionally puzzled at things I thought I was pretty direct about. Honestly though I don't like writing. Finding stuff out about hardware is fun. Weaving it into a coheren
19.
by clamchowder 2y ago
iGPUs like the ones in PHX/MTL have to go into handhelds and ultrabooks, so they're going to be power and thermally limited in before 2-4 MB of cache + LPDDR5 becomes a major bottleneck. Now if you can give the iGPU a 80W power bu
20.
by clamchowder 2y ago
I simply meant it was ambitious compared to prior Intel iGPUs, especially stuff like Skylake GT2 where you could be playing at 720P low and still not get 30 FPS. The chiplet strategy is kind of ambitious too because there's power overh
21.
by clamchowder 2y ago
4K 120..."There's the bar!" - By ambitious I meant Intel's serious about getting competitive gaming performance in the handheld or thin/light laptop category. MTL's iGPU is ambitious compared to older standard
22.
by clamchowder 2y ago
(author here) I appreciate the feedback, but I have trouble understanding where you're coming from. "what exactly makes it ambitious?" I thought I outlined that it was much more powerful than Intel's prior (RPL) iGPUs bo
23.
by clamchowder 2y ago
Well for me it was a matter of how much time it took. I spent enough time understanding the Central Processor with all the weird CDC-specific terms. I had to reread several times before I realized Increment instructions did load/store.
24.
by clamchowder 2y ago
I don't know if the CDC 6600 can be considered superscalar. I called it scalar because it can never issue more than one instruction per cycle, and can thus never sustain faster-than-scalar execution. If you use a different definition o
25.
by clamchowder 2y ago
Be sure to check out the training manuals like http://www.bitsavers.org/pdf/cdc/Tom_Hunter_Scans/6600_CPU_T... or http://www.bitsavers.org/pdf/cdc/Tom_Hunter_Scans/6600_CPU_T...
26.
by clamchowder 2y ago
The original Pentium was the first superscalar x86 CPU. Superscalar just means you can execute faster than scalar (one instruction at a time), and the P5 could theoretically sustain 2 IPC. Of course it was in-order so cache misses would lik
27.
by clamchowder 2y ago
Have you considered the date (4/1)? Maybe that has something to do with why an article about a 1960s thing is written in present tense? If describing how an architecture works is "brochure voice" then I guess pretty much any
28.
by clamchowder 2y ago
That's an interesting take considering I read the old CDC brochures and docs, and wrote the article using the equivalent modern terms. For example, what their training manual calls "third-order conflicts" are called WAR (writ
29.
by clamchowder 3y ago
The 8+ runs at slightly faster clocks and has a smaller die. Somehow TSMC's 4 nm is better than Samsung's 4 nm. But yeah everything I wrote there should be applicable to the Snapdragon 8 Gen 1 as well, just without the 10% GPU clo
30.
by clamchowder 3y ago
Author here. > I can see why they described it as a '5 entry load buffer' for instance but it's not really accurate to the true microarchitecture. That's what it looks like to software. I can put 5 loads between two o

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