caisley

6 ms·

1.
by caisley 8mo ago
Wow, awesome thanks for the details! I have once or twice on projects added extra gates as fillers in some 28nm mixed-signal designs for metal layer re-work, but I had no idea that in larger digital teams there was also the practice of addi
2.
by caisley 8mo ago
Modern commercial image sensors are made in process nodes down to 28nm [0], and for visible light have pixels measuring 0.7-1.5 μm. At [0] there a diagram which gives a feel for what technology nodes are available and used for different app
3.
by caisley 8mo ago
Can I ask how often you guys end up doing gate-level netlist ECOs, instead of re-running synthesis when you're close to a deadline? Also, post-fabrication, if a mistake is found, have you been able to fix it just with a new M1 or M2 ma
4.
by caisley 8mo ago
Hey, I'm not a system-level digital designer, but for government-level initiatives to provide 130nm and 65nm fabs for public benefit, yes it exists! From the 2025 Free Silicon Conference: https://wiki.f-si.org/index.php
5.
by caisley 8mo ago
I work in custom CMOS image sensor design, targeting scientific imaging applications like electron microscopes, X-ray microscopy, and detectors for high-energy physics. Our designs aren't that cost sensitive from a unit cost perspectiv
6.
by caisley 8mo ago
You're right that most professional designers historically haven't cared about open source tooling. But this is starting to change, largely because of the recent existence of open PDKs and the creation of better open tools like Op
7.
by caisley 8mo ago
Yes, actually 180 nm still represents a sizable amount of the market, in terms of volume! In more niche applications where chips contain lots of analog functionlity, you can still find plenty of designs being done in 180, 130, 110, and 65 n