azonenberg

7 ms·

1.
by azonenberg 6mo ago
Late to the party here but I didn't see until now. Looking at the layout I'm very confident this controller is fully analog, with just a few gates of digital doing control stuff. There's only a few dozen to maaaaybe low hundr
2.
by azonenberg 1y ago
You could build an NTP server with much less horsepower (and of course without all of the high speed I/O etc). The ones from Leo Bodnar are decent.
3.
by azonenberg 1y ago
Yeah it's always tricky to decide how much detail to include in these posts. If I had gone on a whole explanation of the full 7 series GTX clocking architecture the post would easily have been another few pages in length.
4.
by azonenberg 1y ago
Yep. Although given all of the bugs, I don't recommend anyone try to build one without forking and making substantial design changes :)
5.
by azonenberg 1y ago
Those addresses all make sense, as 0x4000 - 4fff appears to be where the 8051 has its RAM mapped (all of the peek/poke addresses used for accessing serdes fields are on the high end)
6.
by azonenberg 1y ago
I avoid vendor toolchains and BSPs just because of how buggy they are. From my perspective, it's much better to reproduce a bug with a 20-line C or assembler file that compiles with upstream gcc, completely ruling all of their custom s
7.
by azonenberg 1y ago
I did not like that part of it. Personally I've standardized on just three STM32 parts: * L031 for throwaway-cheap stuff where I'm never going to do field firmware updates (so no need to burn flash on a proper bootloader) and just
8.
by azonenberg 1y ago
I don't think I've ever used a ST part without reporting a bunch of datasheet errors. I haven't been bit by an undocumented silicon bug, but I step on documented STM32H7 bugs on a pretty regular basis and there are some poor
9.
by azonenberg 1y ago
This is why I used a VSC PHY. After they bought Microsemi (and Vitesse as a division of Microsemi) it looked like the only viable option to get a QSGMII PHY since all the other players were much worse. When I first started the project in 20
10.
by azonenberg 1y ago
Yes, Vitesse had been on my "naughty list" of companies that were permanently banned from getting a design win from me because of refusing to share any docs or sell parts at distributors or other engineer-hostile practices popular
11.
by azonenberg 1y ago
I have not used anything but arm-none-eabi-gcc for STM32s from day one. Never even installed CubeMX or any other ST software.
12.
by azonenberg 1y ago
No idea, the high power consumption and latency of >1000baseT were such that I've never had any interest in anything newer in baseT land. At home I run 10/100/1000baseT, 10Gbase-SR, 40Gbase-SR4, and am just beginning to pr
13.
by azonenberg 1y ago
The board-level architecture is going to be super simple as big FPGA designs go: * XCKU5P in the middle * 12x GTYs routed to 4x Samtec ARF6 connector for the line cards * 2x GTYs routed to 2x SFP28 uplinks * RGMII to back panel management P
14.
by azonenberg 1y ago
You're going to at least want to AC couple through some capacitors to avoid problems with common mode / RX bias issues between the different PHYs. But if it's on-mobo you don't need to have as much of a fault voltage rat
15.
by azonenberg 1y ago
For context of how lightweight this is, an -O3 release build of my entire firmware on the management processor right now (including the sshd, hardware drivers, TCP/IP stack, the CLI itself, all of the code to query the supported set
16.
by azonenberg 1y ago
The code is at https://github.com/azonenberg/staticnet but I've intentionally avoided over-publicizing it since it hasn't had any kind of third party security review. As of now it's functional enough I&#
17.
by azonenberg 1y ago
The overall system will be powered by 48V DC on a 6-pin Molex Mini-Fit Jr connector, then stepped down to 12V by a 48->12V intermediate bus converter I've previously designed and characterized ( https://serd.es/2024&#
18.
by azonenberg 1y ago
I've wargamed how I'd backdoor an FPGA even given the ability to make a completely new mask set from a fork of the original CAD files, and it's really difficult. You'd either have to add an enormous amount of logic or ha
19.
by azonenberg 1y ago
There are no blobs I'm aware of anywhere that are actually running in the system. The STM32s have a small boot "ROM" burned into a write-protected region of flash but I have it jumpered so I boot from main user flash, not t
20.
by azonenberg 1y ago
This is not going to be cheap. That was never the goal. In low volume when you combine several custom multilayer boards, custom powder-coated sheet metal work, etc even if you allow for the practically-free recycled FPGA this is going to pr
21.
by azonenberg 1y ago
This project dates back to circa 2013 when at the time, there was nothing available in that class without NDAs. Once I got set on the path of going custom I didn't want to back off from the challenge even if an easier path became avail
22.
by azonenberg 1y ago
The plan is 96 ports total for my own use, split across two 48-port 1U switches. And that's something that is now well within reach: I have the power boards assembled and ready to go, I have the FPGAs and PHYs and (not populated) line
23.
by azonenberg 2y ago
I have some obviously reballed (but well done) aliexpress XCKU5P's that I got for $55 a while back. Haven't tested yet but the price was so good I couldn't resist.
24.
by azonenberg 2y ago
It's a documented errata, 2.6.1 on page 8 of ES0491.
25.
by azonenberg 2y ago
Yeah but again, we're talking about the FMC here not the OCTOSPI. Have you hit issues with the FMC? From what other people are telling me, the OCTOSPI is full of land mines and the FMC is pretty decent. The worst errata I've encou
26.
by azonenberg 2y ago
That can't be memory mapped, so I'd need to rewrite my KVS code which currently expects to be able to return a pointer to the raw on-flash image of the config data. Doable but a pain.
27.
by azonenberg 2y ago
Where are you getting them for $2.50?? The XC7Z010-1CLG225C is $74.83 at Digikey in qty 1. Checking sketchier places Win-Source has the CLG400 package for $22.20 and even the cheapest aliexpress seller wants $4.84 for something marked as a
28.
by azonenberg 2y ago
But if I can memory map the FPGA via the FMC, I can simply put an APB memory mapped QSPI controller on the FPGA and store my config there, using the same flash for the FPGA bitstream as well. This saves a chip on the board, reduces the amou
29.
by azonenberg 2y ago
I have some RT1176's in my "to try" pile. The big thing holding me back was that their crypto accelerators were all locked behind NDAs (a dealbreaker for F/OSS work) while the ST ones are documented in the freely downloa
30.
by azonenberg 2y ago
As far as using QSPI memory, one thing I have planned (and will be thoroughly testing) is using an external SPI flash as configuration data storage. Right now if I want to store any nonvolatile settings with power loss protection I need to

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