avianes

8 ms·

1.
by avianes 2y ago
> I understood it is that a single instruction is executed on a 16-wide SIMD unit, thus processing 16 elements/threads/lanes simultaneously (subject to execution mask of course). This is what I mean by "in lockstep".
2.
by avianes 2y ago
> In an operand-collector architecture the threads are still executed in lockstep. > [...] > It is my understanding that you need to synchronize threads when accessing shared memory. Not sure what you mean by lockstep here. When an
3.
by avianes 2y ago
> GPUs are massively parallel devises, they need to keep the scheduler and ALU logic as simple and compact as possible The simplest hardware implementation is not always the more compact or the more efficient. This is a misconception, ex
4.
by avianes 2y ago
Modern chip designs have an enormous amount of logic and therefore standard-cells. And when you are dealing with a huge amount of cell all together, it quickly becomes unmanageable, syntheses tools runtime explode, quality of results declin
5.
by avianes 2y ago
Also, note that: - There is only one Zero (encoded as 0x00), no negative-zero - There is only one NaN (encoded as 0x80)
6.
IEEE FP8 Formats for Machine Learning (Draft) [pdf](github.com)
13 points by avianes 2y ago|3 comments
7.
by avianes 3y ago
Are you aware that x86 and ARM/POWER/RISCV memory consistency model are really different? You can encounter very sneaky multitreading bug when running on ARM/POWER/RISCV a program that you have only tested on x86. Apple
8.
by avianes 3y ago
Well, first of all, because it shows no results after +10 years. There is definitely no indication that it will work someday. And above all because there are too many choices that are too specific, outdated and too exotic. (e.g. the split-s
9.
by avianes 3y ago
Not sure what is exactly your thought, since the optimizations you quote don't really takes advantage of any exposed optimization feature of the language. Are your asking why we could not expose optimization feature (e.g. branch hint t
10.
by avianes 3y ago
> unless the compiler devs are working for the same company that makes the CPU Every CPU manufacturing company have a compile team. > This will never work VLIW processors do work, and for a while now. This type of architecture perform
11.
by avianes 4y ago
You could do unary encoding in a parallel register (and conversely binary encoding using a serial bit stream). The essence of unary encoding is that the number is encoded by the number of bits set to 1 in the word, and not the position of t
12.
by avianes 4y ago
Building a x86/ARM/RISC-V desktop or server class CPU core is more about the microarchitecture. And RISC-V is an ISA, which is a part of the architecture not the microarchitecture. "Ecosystem" here refers to: the compile
13.
by avianes 4y ago
> Separate FP registers - This looks to have started when FPUs were optional and/or physically separate, but that's no longer the case. Using a separate register set for FP is not just about making floats optional. It also allo
14.
by avianes 4y ago
> And again, your intuition about power costs here is just simply wrong. Instruction decode is Simply Not a major part of the power budget of a modern x86 CPU. It's not. I never said that instruction decode was a major part of the p
15.
by avianes 4y ago
> Uh... yes you do? How else do you think it works? No, I literally explain it in my first answer. The part about "1590 decoders" is irrelevant since a misunderstood your message (thinking that you are talking about using 16 de
16.
by avianes 4y ago
> Um... wat? No CPU tries to decode 99 bytes of memory in a cycle Actually, no x86 processor decodes 8 instructions in parallel. This is an example to illustrate how the number of possible offsets scales with 15 instruction lengths. >
17.
by avianes 4y ago
The difficulty is not to decode a single instruction, the difficulty is to decode multiple instructions in parallel (let's say from 5 to 8 instructions in parallel). In a modern high performance processor instructions are decoded in ba
18.
by avianes 4y ago
Ok, but then what does the dev do if it fails? It sounds like you want to use the cache as a private local memory near the core, this is called a scratchpad memory. And to maintain the scratchpad memory a DMA is usually used. It is much mor
19.
by avianes 4y ago
> why not allow the ISA to query[1] if an L1 access is currently viable (enabling dispatch to different static schedules)? I guess you think of an access that is initiated, with an associated code that runs once the access is completed
20.
by avianes 4y ago
AFAIK C906 is not open-source. The open-source variant of C906 is called OpenC906, and we don't know the eventual difference between C906 and OpenC906.
21.
by avianes 4y ago
Another typical use is embedding a public-key in an application or firmware.
22.
by avianes 4y ago
> And here's the million dollar idea, to verify you'd need to destructively inspect your chips at EOL to verify you haven't been screwed over. Anyone wants to start a business? it only protects against backdoor injection
23.
by avianes 4y ago
> If I'm understanding correctly, this allows us to view (previously obfuscated) code that runs on certain (recent-ish) Intel processors? Yes, but this "code" is the Intel microcode. In a modern processor, instructions a
24.
by avianes 4y ago
> But you’re really getting what the memory controller decides to give you. Yes, here the memory is read through a debug bus. > I could design a memory controller with landmines, as in “if you ask for 0x1234 I will go into a mode wher
25.
by avianes 4y ago
> Which machine language is the microcode written in? The mirocode is generally a sequence of uOps. But in Intel's case, there seems to be a more complex mechanism, called XuCode, that generates the uOps sequence. The XuCode ISA see
26.
by avianes 4y ago
> Or run Linux on ARM, and hope that noone will find similar exploits in the ARM architecure It's a micro-architecture exploit, nothing specific to the x86 architecture. I highly suspect that some ARM implementations are also vuln
27.
by avianes 4y ago
> There are a few cross-lane shuffles / reduce instruction but it seems to me that those would be handled in a dedicated execution unit. (they are not really the fast-path/common case) Yes, you essentially need a (kind of) cr
28.
by avianes 4y ago
Yes, the issue raised definitely not prevents a high-performance implementation. But it's still interesting to ask ourselves if this is not an unnecessary cost? The concern I have here is that to deal with this question you need very g
29.
by avianes 4y ago
I would be curious to know which RISC-V V implementation the author is talking about. > If you imagine how a physical CPU or GPU has to be constructed in order to do large multi-input operations (...) You can imagine these inputs as bei
30.
by avianes 4y ago
DIV that traps is for binary compatibility, not performance.

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