ashtonsix

7 ms·

1.
by ashtonsix 9mo ago
No, but it could help people build those synthesis tools much faster. P4Synth takes a (mathematical) group of functions/expressions and finds strong candidate implementations for every class in that group. Then, as long we have a fast
2.
P4Synth: 1000x faster function synthesis vs. SAT(github.com)
1 points by ashtonsix 9mo ago|2 comments
3.
46% smaller OLAP indexes with BSP-style bitsets(github.com)
3 points by ashtonsix 11mo ago|0 comments
4.
BSP-inspired bitsets: 46% smaller than Roaring (but probably not faster)(github.com)
2 points by ashtonsix 11mo ago|0 comments
5.
by ashtonsix 11mo ago
Oh right. That's sensible enough. Makes total sense to parallelise across multiple cores. I wouldn't expect a strictly linear speed-up due to contention on the memory bus, but it's not as bad as flat-lining after engaging 2-3
6.
by ashtonsix 11mo ago
Haha... GPUs are great. But do you mean to suggest we should swap a single ARM core for a top-line GPU with 10k+ cores and compare numbers on that basis? Surely not. Let's consider this in terms of throughput-per-$ so we have a fungibl
7.
by ashtonsix 11mo ago
Mm, I used that exact writeup as a reference to implement this algorithm in WebGL 3 years ago: https://github.com/ashtonsix/webglc/blob/main/src/kernel/sca... It even inspired the alternative &
8.
by ashtonsix 11mo ago
I just did a mini-ablation study for this (prefix sum). By getting rid of the cross-block carry (16 values), you can increase perf from 19.85 to 23.45 GB/s: the gain is modest as most performance is lost on accumulator carry within the
9.
by ashtonsix 11mo ago
Each Grace CPU has multiple cores: https://www.nvidia.com/en-gb/data-center/grace-cpu-superchip This superchip (might be different to whichever you're referring to) has 2 CPUs (144 cores): https://
10.
by ashtonsix 11mo ago
Oh neat. I have some related unpublished SOTA results I want to release soon: PEF/BIC-like compression ratios, with faster boolean algebra than Roaring Bitsets.
11.
by ashtonsix 11mo ago
By typical I imagined adoption within commonly-deployed TSDBs like Prometheus, InfluxDB, etc. GB/GH are actually ideal targets for my code: both architectures integrate Neoverse V2 cores, the same core I developed for. They are superch
12.
by ashtonsix 11mo ago
The weirdness probably comes from heavy use of "SIMD intrinsics" (Googleable term). These are functions with a 1:1 correspondence to assembly instructions, used for processing multiple values per instruction.
13.
by ashtonsix 11mo ago
If the data is already in GPU memory, yes. Otherwise you'll be limited by the DRAM<->VRAM memory bottleneck. When we consider that delta coding (and family), are typically applied as one step in a series of CPU-first transforms a
14.
Prefix sum: 20 GB/s (2.6x baseline)(github.com)
89 points by ashtonsix 11mo ago|32 comments
15.
by ashtonsix 1y ago
I'm assuming you're referring to BFM/EXTR? NEON absolutely improves here. The core I developed on (Neoverse V2) has 4 SIMD ports and 6 scalar integer ports, however only 2 of those scalar ports support multicycle integer oper
16.
by ashtonsix 1y ago
Oh nice! Axion C4A and Graviton4 use the same core (Neoverse V2), so the performance difference is due to factors like clock speed and power management. I used a geometric mean to calculate the top-line "86 GB/s" for NEON pac
17.
by ashtonsix 1y ago
From the working set size and knowledge of hardware cache behaviour. Whenever you access data from memory not already in-cache it's copied four times: to L3, L2, L1 and to CPU registers. As you access data, the hardware evicts old cach
18.
by ashtonsix 1y ago
If you have an array of numbers with a known upper-bound, such as enums with 8 possible values (representable with 3 bits), and a memory-bound operation on those numbers eg, for (int i; i < n; i++) if (user_category[i] == 0) filtered.pus
19.
by ashtonsix 1y ago
Not having (1 << k) - 1 as a single instruction sucks when it HAS to be in a hot loop, but you can usually hoist this to the loop prolougue: my stuff uses dummy inline assembly hints to force compilers to do this `asm volatile("&
20.
by ashtonsix 1y ago
Good work, wish I saw it earlier as it overlaps with a lot of my recent work. I'm actually planning to release new SOTAs on zigzag/delta/delta-of-delta/xor-with-previous coding next week. Some areas the work doesn't
21.
by ashtonsix 1y ago
Nice article! I personally find the ARM ISA far more cohesive than x86's: far less historical quirks. I also really appreciate the ubiquity of support for 8-bit elements in ARM and the absence of SMT (make performance much more predict
22.
by ashtonsix 1y ago
Thank you so much for attempting a reproduction! (I posted this on Reddit and most commenters didn't even click the link) For the baseline you need SIMDe headers: https://github.com/simd-everywhere/simde/tree&
23.
86 GB/s bitpacking with ARM SIMD (single thread)(github.com)
132 points by ashtonsix 1y ago|29 comments
24.
Webglc: Gpgpu for Web Browsers(github.com)
2 points by ashtonsix 5y ago|0 comments
25.
Can you sell science? With NFTs, yes(ashtonsix.substack.com)
2 points by ashtonsix 6y ago|0 comments
26.
Minify Your GraphQL Queries(npmjs.com)
1 points by ashtonsix 7y ago|0 comments
27.
Cycleprop, a new approach to deep learning(github.com)
3 points by ashtonsix 7y ago|0 comments
28.
by ashtonsix 8y ago
Oh, it's $0.36/hour for salamander. the equivalent on gcp (n1-16-standard with attached k80) is $0.29/hour. though as you said, Salamander is easier to get started with (just 1 click after signing up!) ps: i'm the creato
29.
Deep Learning Generalisation Game(ashtonsix.com)
1 points by ashtonsix 8y ago|0 comments
30.
by ashtonsix 8y ago
Yes, I built it this way to reduce financial risk on my side; for instance, if lots of users suddenly sign up and the AWS bill is really big. I'm making the onboarding process smoother this weekend, so after Monday all new users will h

More ›