adapteva

6 ms·

1.
Why aren't there more FPGA companies?(zeroasic.com)
3 points by adapteva 3mo ago|0 comments
2.
Pavona vs. OpenTitan, why the hard fork?(pavona.org)
2 points by adapteva 4mo ago|1 comments
3.
by adapteva 4mo ago
Does anyone have the backstory on this?
4.
by adapteva 4mo ago
Exactly why we zero asic is making Platypus devices open bitstream and all tooling foss from day one...to protect the world against future evil/dumb version of ourselves. https://www.zeroasic.com/platypus https:/
5.
Starting a Chip Design Revolution(zeroasic.com)
1 points by adapteva 10mo ago|0 comments
6.
by adapteva 1y ago
Thank you, comment made my day:-)
7.
by adapteva 1y ago
Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86. Thierry's synthesis scripts are really very cle
8.
by adapteva 1y ago
Documentation can be found in two places. What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest&#x
9.
by adapteva 1y ago
I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic
10.
Open source synthesis best FPGA vendor tools(zeroasic.com)
2 points by adapteva 1y ago|0 comments
11.
by adapteva 1y ago
No strings common share purchase means cash in hand, which implies Intel can spend it on any operational cost, including buying billions in TSMC wafers (which they already do).
12.
by adapteva 1y ago
Any strings attached? If not, ironically a big chunk of those US tax payer dollars will likely end up in Taiwan/TSMC.
13.
by adapteva 1y ago
Weird title, makes it seem like a reveleation. There have been numerous Viking treasures discovered in Sweden with traces from the the Islamic world and it's well known that they were all over England as well. https://en.wik
14.
Learning Analog System Design(spectrum.ieee.org)
2 points by adapteva 1y ago|0 comments
15.
List of Semiconductor Startups(github.com)
1 points by adapteva 1y ago|0 comments
16.
by adapteva 1y ago
The only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000). We'll see w
17.
by adapteva 1y ago
First off, this is an eFPGA core not a chip. It's intended for folks who want to build their own ASICs with a small amount of embedded FPGA logic. The LUT is a boring text book 4-LUT. Fancier versions are in the works. The point of the
18.
Platypus: Developing the "RISC-V for FPGAs"(zeroasic.com)
5 points by adapteva 1y ago|0 comments
19.
by adapteva 2y ago
Oh no, we have lost another giant! Very few people in the world know the gratitude she is owed. I doubt Nvidia and the other fabless companies would exist without her contribution. I met her through DARPA in 2018 [ref] and I later reached o
20.
by adapteva 2y ago
Yup, got an cold email from them. Marked it as spam and never heard from them again...
21.
by adapteva 2y ago
Yes, that's a great idea, but none of the projects you mentioned are ready for production. Who will find the building of these products?
22.
by adapteva 2y ago
Yes
23.
by adapteva 2y ago
Makefiles can work for simple builds. Logik being Python based can do so much more: automated metrics gathering, conditional flows, parallel execution, error handling, dependency management
24.
by adapteva 2y ago
Haha, cool to see this on HN.:-) Yosys and vpr is clearly doing the heavy lifting here...the novelty here is the fact that an FPGA startup is giving public access to the fpga pre production and is opening the bit stream format. This hasn&#x
25.
Show HN: Build Your Own Chip(github.com)
1 points by adapteva 2y ago|0 comments
26.
Low latency (microsecond) communication frameworks(github.com)
1 points by adapteva 3y ago|0 comments
27.
RFC: A Universal Memory Interface(github.com)
1 points by adapteva 3y ago|0 comments
28.
by adapteva 3y ago
Absolute statements are bad.
29.
by adapteva 3y ago
Ten years too early.... https://parallella.org/2015/05/25/how-the-do-i-program-the-p...
30.
by adapteva 3y ago
There is no guarantee that it will, but... case #1. If you truly have something custom IP, we could save time/effort by only chipletizing that part rather than working on the while SoC. The design and verification is an exponential fun

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