_chris_

8 ms·

1.
by _chris_ 1mo ago
1B through 15B variable length instruction mess, for one. Which still yields a worse than average 4-5B per instruction average.
2.
by _chris_ 1y ago
Longer time horizon -- mortage inflates away. In the short-term, only need to beat the property tax bill, especially if the interest rate is <3% and the property is increasing in value faster than that.
3.
by _chris_ 1y ago
A BPU needs to predict 3 things: - 1) Is there a branch here? - 2) If so, is it taken? - 3) If so, where to? If a conditional branch is never taken, then it's effectively a NOP, and you never store it anywhere, so you treat
4.
by _chris_ 1y ago
> A lot of the time this is a hint to the compiler on what the expected paths are so it can keep those paths linear. IIRC, this mainly helps instruction cache locality. The real value is that the easiest branch to predict is a never-take
5.
by _chris_ 1y ago
> The thing holding back VLIW was compilers were too dumb That’s not really the problem. The real issue is that VLIW requires branches to be strongly biased, statically, so a compiler can exploit them. But in fact branches are very dynam
6.
by _chris_ 2y ago
Wouldn’t a smart tv do something ... smarter than just using the default dns given to it by the network? I’m not up to speed on this stuff but I thought pihole only blocked the simplest stuff from devices that play nice?
7.
by _chris_ 2y ago
It’s not that hard to debug— your signal names and register names all carry through. Sure, lots of temp wires get generated but that’s never where your bug is.
8.
by _chris_ 2y ago
> allow to select the purchase price within the last 2 years I don't think that's true. My reading of that is "you lock in the price on your start date and can keep that for the next 2 years going forward". That doe
9.
by _chris_ 3y ago
> I’d be interested in understanding why the compilers never panned out but have never seen a good writeup on that. Or why people thought the compilers would be able to succeed in the first place at the mission. It's a fundamental
10.
by _chris_ 3y ago
> L1i matters, people! RISC-V consistently wins on L1i footprint. The complaining is about number of dynamic instructions ("path length"), which can hit you if you don't fuse. Of course, path length might not actually be
11.
by _chris_ 3y ago
> > Cascade discovered 4 bugs in BOOM and CVA6 that produce wrong output val- ues regardless of the microarchitectural state > These are unacceptable bugs, showing a lack of architectural tests. It means no one ever ran those instr
12.
by _chris_ 3y ago
Looks like from Appendix D that only 2 bugs were found in BOOM: > 1. Inaccurate instruction count when minstret is written by software I don't know what that means, but having minstret written by software was definitely not somethin
13.
by _chris_ 3y ago
If you want to do some further archeology, check out the SMIPS ISA, which I believe dates back to 2005 (which itself gradually evolved from the T0/Scale/6.371 MIPS ISAs; and the earliest, T0, was derived from MIPS-II).
14.
by _chris_ 3y ago
I also get a permission error: but I think this ( https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris... ) is the same file, and functionally the same as the fa11 version? I think RDNPC is what I was t
15.
by _chris_ 3y ago
To add to this, Andrew et. al. at Berkeley built SPARC cores, so they were well aware of what it took to implement hardware to run SPARC software. I believe some of the really annoying challenges were at the system/privileged architect
16.
by _chris_ 3y ago
I believe early on there was a change to a pre-AUIPC instruction due to potential infringement fears (for PC-relative indexing); but everything else was understood to be following well-worn paths.
17.
by _chris_ 3y ago
And adds non-destructive instructions. > "In addition, legacy integer instructions now can also use EVEX to encode a dedicated destination register operand – turning them into three-operand instructions and reducing the need for ext
18.
by _chris_ 4y ago
> their clean orthogonal instruction encoding is so inefficient (e.g. it wastes a lot of instruction cache) Perhaps, although ARMv8 is fixed 4 bytes and x86-64 averages more than 4 bytes an instruction despite each x86 instruction mappin
19.
by _chris_ 5y ago
Custom opcodes have a protected spot in the opcode map; but there's nothing that prevents two different CPUs from using the same custom opcode pattern to mean two different instructions. Conceivably, you could trap, look up something l
20.
by _chris_ 5y ago
Very different. RISC-V's vectors (RVV) are "variable length", so the programmer can request a length and the machine tells you what it can give you. Different machine versions can change the underlying vector size and the cod
21.
by _chris_ 5y ago
> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to. That's inefficient for an FPGA softcore; wires are too expensive, CAMs are straight up awful, and memory lat
22.
by _chris_ 5y ago
> I wonder if we're ever going to see a 8wide decoder RISC-V. Considering there are 6-wide x86 cores on the market, I wouldn't be too concerned about RISC-V going wide. The instruction length decode is a 2-bit dependency chai
23.
by _chris_ 5y ago
Lying all the time has consequences.
24.
by _chris_ 5y ago
>> The RISC-V vector registers are in a separate register file not shared with the scalar floating point registers. > Honestly... in hardware, they probably are actually in the same register file. It just now means you have two se
25.
by _chris_ 5y ago
It looks like RVV will be going up for ratification this summer, so ( https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado... ) is pretty close to the final version.
26.
by _chris_ 5y ago
> Quote from their white paper: "this is not friendly to deeply pipelined processor architecture." There is zero reason you can't rename the VL register. "Speculating" that it doesn't change is only one desi
27.
by _chris_ 5y ago
It takes years for tooling to improve and for industry designs to start making it out into the world. As more designs make it into end-users' hands, the tooling has even more motivation to improve. I feel like that slow evolution can m
28.
by _chris_ 6y ago
x86-64 code density is more than 4 bytes / instruction.
29.
by _chris_ 6y ago
>> Is there not any wisdom to giving rural areas a counterweight to heavily populated urban areas? > The founders thought so. It's called the US Senate. No, they were trying throw a bone to states like Connecticut, Rhode I
30.
by _chris_ 6y ago
But if you sell out after Series A you should have a ton of equity still left with little dilution? In this case, it looks like they did a $50M Series A and a $240M Series B. IIRC, 5x is respectable, but I can imagine the VCs might be on mu

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