MootWoop

7 ms·

1.
by MootWoop 11y ago
Sounds great! I'll do my best to answer all questions :-) My email is matthieu.wipliez@synflow.com
2.
by MootWoop 11y ago
Matthieu, co-founder of Synflow here. Maybe I could help? Don't hesitate to send me an email!
3.
The problem with FPGAs [and how to solve it](blog.synflow.com)
5 points by MootWoop 11y ago|0 comments
4.
The Secret to Smart Groups: It's Women(theatlantic.com)
3 points by MootWoop 11y ago|0 comments
5.
by MootWoop 11y ago
Yep, I'm Matthieu! You can send me an email at matthieu.wipliez at synflow.com
6.
by MootWoop 11y ago
> Today's beginners don't make the tools. Not necessarily, I am a beginner in hardware design, and I am creating a new programming language and IDE for hardware design. > The academics who trained us at uni had never worked
7.
by MootWoop 11y ago
Good point about the reasons of productivity leaps. Funnily enough, I recall that one of the main selling points of Java was portability (the famous "Write Once Run Everywhere"), even though C was already supposed to be portable;
8.
by MootWoop 11y ago
To whomever downvoted this: would you mind telling me why? Have I offended you in some way? Is it because of the criticism of the hardware industry? Or the sarcasm?
9.
by MootWoop 11y ago
2. I am curious to hear what you think about our solution of wrapping existing VHDL/Verilog in an external task in Cx? http://cx-lang.org/documentation/tasks#external
10.
by MootWoop 11y ago
> The bugs are not due to language generally. That's like saying that buffer overflows are not due to how strings are represented in C. Yes a bug is the programmer's fault, but languages can make it harder to have bugs in the f
11.
by MootWoop 11y ago
> For an engineer it does not matter about the language that describes the circuit. [...] Typing it in is the easiest part. Well... once upon a time, people were writing software with assembly, and they probably didn't care about th
12.
by MootWoop 11y ago
> it looked very promising Thanks! > Reading from a port twice seems to trigger a clock cycle (did I get that right?) You did! It is by design that reading from the same port twice will trigger a clock cycle :-) There are several reas
13.
by MootWoop 11y ago
That's the beauty (and sometimes the curse) of hardware design: it doesn't need a processor to run. You essentially describe an electronic circuit, and "program" (configure would be more appropriate) an FPGA to act like
14.
by MootWoop 11y ago
Interesting, I feel like you would like what we've done with the Cx language at Synflow. Probably the exact opposite of CλaSH, the language is sequential imperative (C-like even) and focuses on making the sequential part easier (Cx sti
15.
by MootWoop 11y ago
Hard to say, it depends on what you consider better. It certainly is more concise than the equivalent Verilog (just like Haskell is more concise than pretty much any language I know). This seems especially true when you want to describe rep
16.
by MootWoop 11y ago
The way I see it, it's Register Transfer Level, just written differently. Instead of writing: @always(clock) counter <= counter + 1; you write: counter = s where s = register 0 (s + 1) per http://hackage.haskell.o
17.
by MootWoop 11y ago
How well HLS does highly depends on the source code (this is in general and not specific to Vivado HLS). If your code is a simple loop over an array and you add a vendor-specific #pragma directive (such as #pragma unroll) the tool will unro
18.
by MootWoop 12y ago
@gothenburg @mng2 I get that you think it's not useful or even it's crazy, especially as both of you seem to be seasoned hardware designers. But as a software guy myself, there's nothing I have found more horrible when learni
19.
by MootWoop 12y ago
Really? Aren't they using VHDL generics/Verilog parameters? Cx supports specialization of entities with this kind of semantics, so you give an instance parameters and the compiler generates specialized code (so there's no mor
20.
by MootWoop 12y ago
Yes it is still in use, and the simulation capabilities are quite advanced! It remains a HDL, better than VHDL and Verilog, so you still have to worry about resetting, clocks and state machine. Just a word of caution the cycle accurate simu
21.
by MootWoop 12y ago
That's a very good point. In fact the main difference in semantics is that Cx code is structured. Sure in VHDL/Verilog you have functions and if statements and loops. But they can only be used to describe combinational logic. Ther
22.
by MootWoop 12y ago
Exactly! Isn't that a breeze? Reset and clock are implicit by default, but you can always override them (change name, set reset synchronous, etc.)
23.
by MootWoop 12y ago
Don't worry, you're not the first to find that this looks similar to Verilog. I have commented about the syntax aspect on EETimes: see http://www.eetimes.com/author.asp?section_id=36&doc_id=13252... It's
24.
by MootWoop 12y ago
Good point, we need to make this clearer I think. We (Synflow) have a compiler and IDE that you can download from https://www.synflow.com The compiler and IDE are open source, and the compiler generates VHDL code. We also have a
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by MootWoop 12y ago
We hope so too :) If somehow Cx doesn't live up to its promises and what you expect from it, please let us know! We're still improving it based on the feedback we get. Thanks!
26.
by MootWoop 12y ago
I think that the philosophy is different, and this implies a lot of things. We wanted to try something different, create a language and IDE that were easy to use rather than make something more or less compatible with C; and we aimed at mak
27.
by MootWoop 12y ago
Thanks! You might be interested by my implementation of SHA-256 in Cx available on Github: https://github.com/synflow/sha-256 It is a toy example (I haven't implemented the pre-processing step), with an architectu
28.
by MootWoop 12y ago
Hi I'm a co-founder of Synflow and author of the website. Sorry if this is not clear about what is open source or not. To answer your question the language, compiler, and IDE are open source: https://github.com/synflow&
29.
by MootWoop 12y ago
Thank you for your insight and suggestions! This example is really a toy implementation to show what the Cx language looks like, so it is not really suited for a robust hardware core. With this example I put the emphasis on how easy it is t
30.
by MootWoop 12y ago
Hi I'm the person who wrote this example. In fact you don't need to check that stop bits are ones because one is the default: when nothing is being written on the line, it is high all the time. This is why it's just a matter

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