Andrey_Filippov

6 ms·

1.
by Andrey_Filippov 3y ago
We do it now with thermal images: https://image-ppubs.uspto.gov/dirsearch-public/print/downloa...
2.
by Andrey_Filippov 9y ago
A focus puller is already built using FPGA+GNU/Linux - https://github.com/Qinematiq
3.
by Andrey_Filippov 10y ago
I think Obama should not just pardon Snowden, but nominate him to a position of NSA director. Snowden is both a top professional and cares about our rights and freedoms. NSA is still needed (in some form) in the real world, and I would defi
4.
by Andrey_Filippov 10y ago
Yes, I'm guilty in DRY violation and I mentioned it in the post - I still manually translate Verilog to Python when go from simulation/debugging to hardware testing/debugging. And we are looking to use a more productive way t
5.
by Andrey_Filippov 10y ago
Yes, you are absolutely right about "repeatedly solved problems", so it is definitly one in the series of "yet another ...". I'll try your program on our project files to see what registers it can extract from it. I
6.
by Andrey_Filippov 11y ago
Scott, you are right, and I try to do it that way (there are many registers in the design with "_ram" suffix. But I did have some problems when Vivado incorrectly inferred small non-registered RAM as Block RAM. I was able to modif
7.
by Andrey_Filippov 11y ago
Thank you, at leas one of "these people" got it. Interesting project, but again - it is still far performance-wise. We really appreciate work of developers of the Free Software toolchain, but we work in a slightly different area a
8.
by Andrey_Filippov 11y ago
What objections do you have to the requirements to release documentation? Similar anti-monopoly laws already exist in other areas. It would make Clifford's job much easier (so you will benefit too), don't you think?
9.
by Andrey_Filippov 11y ago
No single dominating block. Camera has 4 sensor channels (now either 12 bit parallel or Aptina HiSPI) with gamma and histograms, 16-channel DDR3 controller, 4 compressor channels, inter-camera synchronization and high-speed IMU logger. And
10.
by Andrey_Filippov 11y ago
Project uses 84% of Zynq (7030), it will not fit in Lattice :-(
11.
by Andrey_Filippov 11y ago
Not really many are "analog" and we already have GTX model. Some primitives are just buffers, some - memories (block RAM), one PLL. I do not think it is a "rocket science" to create functional models without precise timi